Implementation method of a turbo-code decoder using a block-wise MAP algorithm

Goohyun Park, Sukhyon Yoon, Changeon Kang, Daesik Hong

Research output: Contribution to journalConference article

4 Citations (Scopus)

Abstract

The several implementation methods of the MAP decoder are proposed in this paper. By using the novel time-shared process of a pipe-lined structure, the restriction of recursion process on state metric can be efficiently conquered, and the complexity of the MAP decoder can be reduced to the order of a SOVA (Soft Output Viterbi Algorithm) decoder. And, an efficient structure for the controller is also proposed for cdma-2000 system. The designed MAP decoder using a block-wise MAP algorithm has been implemented in only one 20,000 gate circuit. It has been validated by VHDL, which has been compared with the results of the initial simulation (C programs). The designed decoder has 300 kbps decoding processing ability with 8 times iterations on a FPGA circuit, and just has a deviation of about 0.1 to approximately 0.2 dB over the ideal MAP decoder, even if all hardware environments were considered.

Original languageEnglish
Pages (from-to)2956-2961
Number of pages6
JournalIEEE Vehicular Technology Conference
Volume6
Issue number52 ND
Publication statusPublished - 2000 Dec 1

Fingerprint

Turbo Codes
Turbo codes
Viterbi Algorithm
Viterbi algorithm
Computer hardware description languages
Networks (circuits)
Recursion
Field Programmable Gate Array
Decoding
Field programmable gate arrays (FPGA)
Deviation
Pipe
Hardware
Restriction
Controller
Iteration
Metric
Controllers
Output
Processing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Park, Goohyun ; Yoon, Sukhyon ; Kang, Changeon ; Hong, Daesik. / Implementation method of a turbo-code decoder using a block-wise MAP algorithm. In: IEEE Vehicular Technology Conference. 2000 ; Vol. 6, No. 52 ND. pp. 2956-2961.
@article{a4b29f4ca8b8440d87e1c55e44adb401,
title = "Implementation method of a turbo-code decoder using a block-wise MAP algorithm",
abstract = "The several implementation methods of the MAP decoder are proposed in this paper. By using the novel time-shared process of a pipe-lined structure, the restriction of recursion process on state metric can be efficiently conquered, and the complexity of the MAP decoder can be reduced to the order of a SOVA (Soft Output Viterbi Algorithm) decoder. And, an efficient structure for the controller is also proposed for cdma-2000 system. The designed MAP decoder using a block-wise MAP algorithm has been implemented in only one 20,000 gate circuit. It has been validated by VHDL, which has been compared with the results of the initial simulation (C programs). The designed decoder has 300 kbps decoding processing ability with 8 times iterations on a FPGA circuit, and just has a deviation of about 0.1 to approximately 0.2 dB over the ideal MAP decoder, even if all hardware environments were considered.",
author = "Goohyun Park and Sukhyon Yoon and Changeon Kang and Daesik Hong",
year = "2000",
month = "12",
day = "1",
language = "English",
volume = "6",
pages = "2956--2961",
journal = "IEEE Vehicular Technology Conference",
issn = "0740-0551",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "52 ND",

}

Implementation method of a turbo-code decoder using a block-wise MAP algorithm. / Park, Goohyun; Yoon, Sukhyon; Kang, Changeon; Hong, Daesik.

In: IEEE Vehicular Technology Conference, Vol. 6, No. 52 ND, 01.12.2000, p. 2956-2961.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Implementation method of a turbo-code decoder using a block-wise MAP algorithm

AU - Park, Goohyun

AU - Yoon, Sukhyon

AU - Kang, Changeon

AU - Hong, Daesik

PY - 2000/12/1

Y1 - 2000/12/1

N2 - The several implementation methods of the MAP decoder are proposed in this paper. By using the novel time-shared process of a pipe-lined structure, the restriction of recursion process on state metric can be efficiently conquered, and the complexity of the MAP decoder can be reduced to the order of a SOVA (Soft Output Viterbi Algorithm) decoder. And, an efficient structure for the controller is also proposed for cdma-2000 system. The designed MAP decoder using a block-wise MAP algorithm has been implemented in only one 20,000 gate circuit. It has been validated by VHDL, which has been compared with the results of the initial simulation (C programs). The designed decoder has 300 kbps decoding processing ability with 8 times iterations on a FPGA circuit, and just has a deviation of about 0.1 to approximately 0.2 dB over the ideal MAP decoder, even if all hardware environments were considered.

AB - The several implementation methods of the MAP decoder are proposed in this paper. By using the novel time-shared process of a pipe-lined structure, the restriction of recursion process on state metric can be efficiently conquered, and the complexity of the MAP decoder can be reduced to the order of a SOVA (Soft Output Viterbi Algorithm) decoder. And, an efficient structure for the controller is also proposed for cdma-2000 system. The designed MAP decoder using a block-wise MAP algorithm has been implemented in only one 20,000 gate circuit. It has been validated by VHDL, which has been compared with the results of the initial simulation (C programs). The designed decoder has 300 kbps decoding processing ability with 8 times iterations on a FPGA circuit, and just has a deviation of about 0.1 to approximately 0.2 dB over the ideal MAP decoder, even if all hardware environments were considered.

UR - http://www.scopus.com/inward/record.url?scp=0034515870&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034515870&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0034515870

VL - 6

SP - 2956

EP - 2961

JO - IEEE Vehicular Technology Conference

JF - IEEE Vehicular Technology Conference

SN - 0740-0551

IS - 52 ND

ER -