Abstract
In this paper, we presents efficient hardware design of inter picture prediction in the slim - high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-Time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7.
| Original language | English |
|---|---|
| Title of host publication | ISOCC 2016 - International SoC Design Conference |
| Subtitle of host publication | Smart SoC for Intelligent Things |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 321-322 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781467393089 |
| DOIs | |
| Publication status | Published - 2016 Dec 27 |
| Event | 13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of Duration: 2016 Oct 23 → 2016 Oct 26 |
Publication series
| Name | ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things |
|---|
Other
| Other | 13th International SoC Design Conference, ISOCC 2016 |
|---|---|
| Country | Korea, Republic of |
| City | Jeju |
| Period | 16/10/23 → 16/10/26 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation
Cite this
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Implementation of low complexity inter prediction for IoT systems. / So, Jaehyuk; Mun, Junwon; Oh, Kyungmook; Kim, Jaeseok.
ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., 2016. p. 321-322 7799807 (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Implementation of low complexity inter prediction for IoT systems
AU - So, Jaehyuk
AU - Mun, Junwon
AU - Oh, Kyungmook
AU - Kim, Jaeseok
PY - 2016/12/27
Y1 - 2016/12/27
N2 - In this paper, we presents efficient hardware design of inter picture prediction in the slim - high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-Time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7.
AB - In this paper, we presents efficient hardware design of inter picture prediction in the slim - high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-Time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7.
UR - http://www.scopus.com/inward/record.url?scp=85010366233&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85010366233&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2016.7799807
DO - 10.1109/ISOCC.2016.7799807
M3 - Conference contribution
AN - SCOPUS:85010366233
T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
SP - 321
EP - 322
BT - ISOCC 2016 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -