TY - GEN
T1 - Implementation of low complexity inter prediction for IoT systems
AU - So, Jaehyuk
AU - Mun, Junwon
AU - Oh, Kyungmook
AU - Kim, Jaeseok
N1 - Publisher Copyright:
© 2016 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2016/12/27
Y1 - 2016/12/27
N2 - In this paper, we presents efficient hardware design of inter picture prediction in the slim - high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-Time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7.
AB - In this paper, we presents efficient hardware design of inter picture prediction in the slim - high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-Time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7.
UR - http://www.scopus.com/inward/record.url?scp=85010366233&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85010366233&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2016.7799807
DO - 10.1109/ISOCC.2016.7799807
M3 - Conference contribution
AN - SCOPUS:85010366233
T3 - ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things
SP - 321
EP - 322
BT - ISOCC 2016 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th International SoC Design Conference, ISOCC 2016
Y2 - 23 October 2016 through 26 October 2016
ER -