In-order issue out-of-order execution floating-point coprocessor for CalmRISC32

C. H. Jeong, W. C. Park, T. D. Han, S. W. Kim, M. K. Lee

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

The CalmRISC32 FPU(Floating-Point Unit) is a RISC coprocessor for embedded system applications. It supports IEEE-754 standard single precision floating-point addition, floating-point subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, load, store, etc. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order, if such constraints as data dependency, resource conflict, and exception prediction are resolved. Standard cell-base design techniques were used to reduce design time and expense. The first prototype operated at approximately 70MHz with the worst-case delay in gate level simulation.

Original languageEnglish
Pages195-200
Number of pages6
Publication statusPublished - 2001
Event15th IEEE Symposium on Computer Arithmetic - Vail, CO, United States
Duration: 2001 Jun 112001 Jun 13

Other

Other15th IEEE Symposium on Computer Arithmetic
CountryUnited States
CityVail, CO
Period01/6/1101/6/13

All Science Journal Classification (ASJC) codes

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture

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  • Cite this

    Jeong, C. H., Park, W. C., Han, T. D., Kim, S. W., & Lee, M. K. (2001). In-order issue out-of-order execution floating-point coprocessor for CalmRISC32. 195-200. Paper presented at 15th IEEE Symposium on Computer Arithmetic, Vail, CO, United States.