TY - JOUR
T1 - Incremental Bitline Voltage Sensing Scheme with Half-Adaptive Threshold Reference Scheme in MLC PRAM
AU - Ko, Junyoung
AU - Yang, Younghwi
AU - Kim, Jisu
AU - Oh, Younghoon
AU - Park, H. K.
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 2017 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/6
Y1 - 2017/6
N2 - Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing methods with R-drift tolerance, namely, drift-resilient cell-state metric and incremental bitline voltage (IBV), and compare these sensing methods in terms of the sensing margin and read access time. In addition, we propose a sensing scheme for IBV (IBVSS) with a half-adaptive threshold reference scheme (H-ATRS) to achieve high-R-drift tolerance in severe R-drift conditions with a small layout area for the reference cell. Verification of the IBVSS with H-ATRS is performed by HSPICE simulation using the 0.25-μm model parameters used in the peripheral circuit of Samsung's 20-nm PRAM technology. From the simulation, we find that the IBVSS with H-ATRS achieves more than 1 V of sensing margin under severe R-drift conditions, which ensures stable read operation in the MLC PRAM with 304 ns of sensing time.
AB - Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing methods with R-drift tolerance, namely, drift-resilient cell-state metric and incremental bitline voltage (IBV), and compare these sensing methods in terms of the sensing margin and read access time. In addition, we propose a sensing scheme for IBV (IBVSS) with a half-adaptive threshold reference scheme (H-ATRS) to achieve high-R-drift tolerance in severe R-drift conditions with a small layout area for the reference cell. Verification of the IBVSS with H-ATRS is performed by HSPICE simulation using the 0.25-μm model parameters used in the peripheral circuit of Samsung's 20-nm PRAM technology. From the simulation, we find that the IBVSS with H-ATRS achieves more than 1 V of sensing margin under severe R-drift conditions, which ensures stable read operation in the MLC PRAM with 304 ns of sensing time.
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U2 - 10.1109/TCSI.2017.2654270
DO - 10.1109/TCSI.2017.2654270
M3 - Article
AN - SCOPUS:85011301767
VL - 64
SP - 1444
EP - 1455
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 6
M1 - 7835212
ER -