Input polling arbitration mechanism for a gigabit packet switch

J. W. Son, Y. Y. Oh, H. T. Lee, Jai Yong Lee, S. B. Lee

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.

Original languageEnglish
Pages (from-to)2050-2051
Number of pages2
JournalElectronics Letters
Volume32
Issue number22
DOIs
Publication statusPublished - 1996 Oct 24

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All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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