Input polling arbitration mechanism for a gigabit packet switch

J. W. Son, Y. Y. Oh, H. T. Lee, Jai Yong Lee, S. B. Lee

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.

Original languageEnglish
Pages (from-to)2050-2051
Number of pages2
JournalElectronics Letters
Volume32
Issue number22
DOIs
Publication statusPublished - 1996 Oct 24

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Switches

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Son, J. W. ; Oh, Y. Y. ; Lee, H. T. ; Lee, Jai Yong ; Lee, S. B. / Input polling arbitration mechanism for a gigabit packet switch. In: Electronics Letters. 1996 ; Vol. 32, No. 22. pp. 2050-2051.
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Input polling arbitration mechanism for a gigabit packet switch. / Son, J. W.; Oh, Y. Y.; Lee, H. T.; Lee, Jai Yong; Lee, S. B.

In: Electronics Letters, Vol. 32, No. 22, 24.10.1996, p. 2050-2051.

Research output: Contribution to journalArticle

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