Integration challenges of III-V materials in advanced CMOS logic

R. J.W. Hill, J. Huang, W. Y. Loh, T. Kim, M. H. Wong, D. Veksler, T. H. Cunningham, R. Droopad, J. Oh, C. Hobbs, P. D. Kirsch, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.

Original languageEnglish
Title of host publicationSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2
PublisherElectrochemical Society Inc.
Pages179-184
Number of pages6
Edition6
ISBN (Electronic)9781607683162
ISBN (Print)9781566779586
DOIs
Publication statusPublished - 2012
EventInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting - Seattle, WA, United States
Duration: 2012 May 62012 May 10

Publication series

NameECS Transactions
Number6
Volume45
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceInternational Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting
Country/TerritoryUnited States
CitySeattle, WA
Period12/5/612/5/10

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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