Integration challenges of III-V materials in advanced CMOS logic

R. J.W. Hill; J. Huang; W. Y. Loh; T. Kim; M. H. Wong; D. Veksler; T. H. Cunningham; R. Droopad; J. Oh; C. Hobbs; P. D. Kirsch; R. Jammy

doi:10.1149/1.3700951

Integration challenges of III-V materials in advanced CMOS logic

R. J.W. Hill, J. Huang, W. Y. Loh, T. Kim, M. H. Wong, D. Veksler, T. H. Cunningham, R. Droopad, J. Oh, C. Hobbs, P. D. Kirsch, R. Jammy

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with X_j<10nm, N_D>5× 10¹⁹cm^-3, ρ_c= 6 Ω.μm² and D_it= 4 ×10¹²cV^-1.cm^-2.

Original language	English
Title of host publication	Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2
Publisher	Electrochemical Society Inc.
Pages	179-184
Number of pages	6
Edition	6
ISBN (Electronic)	9781607683162
ISBN (Print)	9781566779586
DOIs	https://doi.org/10.1149/1.3700951
Publication status	Published - 2012
Event	International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting - Seattle, WA, United States Duration: 2012 May 6 → 2012 May 10

Publication series

Name	ECS Transactions
Number	6
Volume	45
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting
Country/Territory	United States
City	Seattle, WA
Period	12/5/6 → 12/5/10

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1149/1.3700951

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Hill, R. J. W., Huang, J., Loh, W. Y., Kim, T., Wong, M. H., Veksler, D., Cunningham, T. H., Droopad, R., Oh, J., Hobbs, C., Kirsch, P. D., & Jammy, R. (2012). Integration challenges of III-V materials in advanced CMOS logic. In Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 (6 ed., pp. 179-184). (ECS Transactions; Vol. 45, No. 6). Electrochemical Society Inc.. https://doi.org/10.1149/1.3700951

Hill, R. J.W. ; Huang, J. ; Loh, W. Y. ; Kim, T. ; Wong, M. H. ; Veksler, D. ; Cunningham, T. H. ; Droopad, R. ; Oh, J. ; Hobbs, C. ; Kirsch, P. D. ; Jammy, R. / Integration challenges of III-V materials in advanced CMOS logic. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2. 6. ed. Electrochemical Society Inc., 2012. pp. 179-184 (ECS Transactions; 6).

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abstract = "The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.",

author = "Hill, {R. J.W.} and J. Huang and Loh, {W. Y.} and T. Kim and Wong, {M. H.} and D. Veksler and Cunningham, {T. H.} and R. Droopad and J. Oh and C. Hobbs and Kirsch, {P. D.} and R. Jammy",

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language = "English",

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series = "ECS Transactions",

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booktitle = "Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2",

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note = "International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting ; Conference date: 06-05-2012 Through 10-05-2012",

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Hill, RJW, Huang, J, Loh, WY, Kim, T, Wong, MH, Veksler, D, Cunningham, TH, Droopad, R, Oh, J, Hobbs, C, Kirsch, PD & Jammy, R 2012, Integration challenges of III-V materials in advanced CMOS logic. in Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2. 6 edn, ECS Transactions, no. 6, vol. 45, Electrochemical Society Inc., pp. 179-184, International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ES Meeting, Seattle, WA, United States, 12/5/6. https://doi.org/10.1149/1.3700951

Integration challenges of III-V materials in advanced CMOS logic. / Hill, R. J.W.; Huang, J.; Loh, W. Y.; Kim, T.; Wong, M. H.; Veksler, D.; Cunningham, T. H.; Droopad, R.; Oh, J.; Hobbs, C.; Kirsch, P. D.; Jammy, R.

Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2. 6. ed. Electrochemical Society Inc., 2012. p. 179-184 (ECS Transactions; Vol. 45, No. 6).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Huang, J.

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AU - Wong, M. H.

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AU - Oh, J.

AU - Hobbs, C.

AU - Kirsch, P. D.

AU - Jammy, R.

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AB - The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.

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Integration challenges of III-V materials in advanced CMOS logic

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