Abstract
The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.
| Original language | English |
|---|---|
| Title of host publication | Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 |
| Pages | 179-184 |
| Number of pages | 6 |
| Edition | 6 |
| DOIs | |
| Publication status | Published - 2012 Nov 19 |
| Event | International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ECS Meeting - Seattle, WA, United States Duration: 2012 May 6 → 2012 May 10 |
Publication series
| Name | ECS Transactions |
|---|---|
| Number | 6 |
| Volume | 45 |
| ISSN (Print) | 1938-5862 |
| ISSN (Electronic) | 1938-6737 |
Other
| Other | International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ECS Meeting |
|---|---|
| Country | United States |
| City | Seattle, WA |
| Period | 12/5/6 → 12/5/10 |
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All Science Journal Classification (ASJC) codes
- Engineering(all)
Cite this
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Integration challenges of III-V materials in advanced CMOS logic. / Hill, R. J.W.; Huang, J.; Loh, W. Y.; Kim, T.; Wong, M. H.; Veksler, D.; Cunningham, T. H.; Droopad, R.; Oh, J.; Hobbs, C.; Kirsch, P. D.; Jammy, R.
Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2. 6. ed. 2012. p. 179-184 (ECS Transactions; Vol. 45, No. 6).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Integration challenges of III-V materials in advanced CMOS logic
AU - Hill, R. J.W.
AU - Huang, J.
AU - Loh, W. Y.
AU - Kim, T.
AU - Wong, M. H.
AU - Veksler, D.
AU - Cunningham, T. H.
AU - Droopad, R.
AU - Oh, J.
AU - Hobbs, C.
AU - Kirsch, P. D.
AU - Jammy, R.
PY - 2012/11/19
Y1 - 2012/11/19
N2 - The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.
AB - The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.
UR - http://www.scopus.com/inward/record.url?scp=84869028552&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84869028552&partnerID=8YFLogxK
U2 - 10.1149/1.3700951
DO - 10.1149/1.3700951
M3 - Conference contribution
AN - SCOPUS:84869028552
SN - 9781566779586
T3 - ECS Transactions
SP - 179
EP - 184
BT - Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2
ER -