@inproceedings{9d8cfa0b2beb45cf83d234889f814593,
title = "Integration challenges of III-V materials in advanced CMOS logic",
abstract = "The superior transport properties of III-V materials make them attractive choices to enable improved performance at low power. This paper examines the integration challenges of III-V materials in advanced CMOS logic at or beyond the 11 nm technology node, and reports VLSI compatible junction, contact and gate stack process modules with Xj<10nm, ND>5× 1019cm-3, ρc= 6 Ω.μm2 and Dit= 4 ×1012cV-1.cm-2.",
author = "Hill, {R. J.W.} and J. Huang and Loh, {W. Y.} and T. Kim and Wong, {M. H.} and D. Veksler and Cunningham, {T. H.} and R. Droopad and J. Oh and C. Hobbs and Kirsch, {P. D.} and R. Jammy",
note = "Copyright: Copyright 2013 Elsevier B.V., All rights reserved.; International Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2 - 221st ECS Meeting ; Conference date: 06-05-2012 Through 10-05-2012",
year = "2012",
doi = "10.1149/1.3700951",
language = "English",
isbn = "9781566779586",
series = "ECS Transactions",
number = "6",
pages = "179--184",
booktitle = "Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 2",
edition = "6",
}