Integration of dual channel timing formatter system for high speed memory test equipment

Jaeseok Park; Ingeol Lee; Young Seok Park; Sung Geun Kim; Kyung Ho Ryu; Dong Hoon Jung; Kangwook Jo; Choong Keun Lee; Hongil Yoon; Seong Ook Jung; Woo Young Choi; Sungho Kang

doi:10.1109/ISOCC.2012.6407070

Integration of dual channel timing formatter system for high speed memory test equipment

Jaeseok Park, Ingeol Lee, Young Seok Park, Sung Geun Kim, Kyung Ho Ryu, Dong Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong Ook Jung, Woo Young Choi, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

Original language	English
Title of host publication	ISOCC 2012 - 2012 International SoC Design Conference
Pages	185-187
Number of pages	3
DOIs	https://doi.org/10.1109/ISOCC.2012.6407070
Publication status	Published - 2012
Event	2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of Duration: 2012 Nov 4 → 2012 Nov 7

Publication series

Name	ISOCC 2012 - 2012 International SoC Design Conference

Other

Other	2012 International SoC Design Conference, ISOCC 2012
Country/Territory	Korea, Republic of
City	Jeju Island
Period	12/11/4 → 12/11/7

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC.2012.6407070

Cite this

Park, J., Lee, I., Park, Y. S., Kim, S. G., Ryu, K. H., Jung, D. H., Jo, K., Lee, C. K., Yoon, H., Jung, S. O., Choi, W. Y., & Kang, S. (2012). Integration of dual channel timing formatter system for high speed memory test equipment. In ISOCC 2012 - 2012 International SoC Design Conference (pp. 185-187). [6407070] (ISOCC 2012 - 2012 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2012.6407070

@inproceedings{5999c2618cce409b8215c85d4ef40725,

title = "Integration of dual channel timing formatter system for high speed memory test equipment",

abstract = "This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.",

author = "Jaeseok Park and Ingeol Lee and Park, {Young Seok} and Kim, {Sung Geun} and Ryu, {Kyung Ho} and Jung, {Dong Hoon} and Kangwook Jo and Lee, {Choong Keun} and Hongil Yoon and Jung, {Seong Ook} and Choi, {Woo Young} and Sungho Kang",

year = "2012",

doi = "10.1109/ISOCC.2012.6407070",

language = "English",

isbn = "9781467329880",

series = "ISOCC 2012 - 2012 International SoC Design Conference",

pages = "185--187",

booktitle = "ISOCC 2012 - 2012 International SoC Design Conference",

note = "2012 International SoC Design Conference, ISOCC 2012 ; Conference date: 04-11-2012 Through 07-11-2012",

}

Park, J, Lee, I, Park, YS, Kim, SG, Ryu, KH, Jung, DH, Jo, K, Lee, CK, Yoon, H , Jung, SO , Choi, WY & Kang, S 2012, Integration of dual channel timing formatter system for high speed memory test equipment. in ISOCC 2012 - 2012 International SoC Design Conference., 6407070, ISOCC 2012 - 2012 International SoC Design Conference, pp. 185-187, 2012 International SoC Design Conference, ISOCC 2012, Jeju Island, Korea, Republic of, 12/11/4. https://doi.org/10.1109/ISOCC.2012.6407070

TY - GEN

T1 - Integration of dual channel timing formatter system for high speed memory test equipment

AU - Park, Jaeseok

AU - Lee, Ingeol

AU - Park, Young Seok

AU - Kim, Sung Geun

AU - Ryu, Kyung Ho

AU - Jung, Dong Hoon

AU - Jo, Kangwook

AU - Lee, Choong Keun

AU - Yoon, Hongil

AU - Jung, Seong Ook

AU - Choi, Woo Young

AU - Kang, Sungho

PY - 2012

Y1 - 2012

N2 - This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

AB - This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

UR - http://www.scopus.com/inward/record.url?scp=84873959803&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84873959803&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2012.6407070

DO - 10.1109/ISOCC.2012.6407070

M3 - Conference contribution

AN - SCOPUS:84873959803

SN - 9781467329880

T3 - ISOCC 2012 - 2012 International SoC Design Conference

SP - 185

EP - 187

BT - ISOCC 2012 - 2012 International SoC Design Conference

T2 - 2012 International SoC Design Conference, ISOCC 2012

Y2 - 4 November 2012 through 7 November 2012

ER -

Integration of dual channel timing formatter system for high speed memory test equipment

Abstract

Publication series

Other

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this