Integration of dual channel timing formatter system for high speed memory test equipment

Jaeseok Park, Ingeol Lee, Young Seok Park, Sung Geun Kim, Kyung Ho Ryu, Dong Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong Ook Jung, Woo Young Choi, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

Original languageEnglish
Title of host publicationISOCC 2012 - 2012 International SoC Design Conference
Pages185-187
Number of pages3
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of
Duration: 2012 Nov 42012 Nov 7

Publication series

NameISOCC 2012 - 2012 International SoC Design Conference

Other

Other2012 International SoC Design Conference, ISOCC 2012
CountryKorea, Republic of
CityJeju Island
Period12/11/412/11/7

Fingerprint

Data storage equipment

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Park, J., Lee, I., Park, Y. S., Kim, S. G., Ryu, K. H., Jung, D. H., ... Kang, S. (2012). Integration of dual channel timing formatter system for high speed memory test equipment. In ISOCC 2012 - 2012 International SoC Design Conference (pp. 185-187). [6407070] (ISOCC 2012 - 2012 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2012.6407070
Park, Jaeseok ; Lee, Ingeol ; Park, Young Seok ; Kim, Sung Geun ; Ryu, Kyung Ho ; Jung, Dong Hoon ; Jo, Kangwook ; Lee, Choong Keun ; Yoon, Hongil ; Jung, Seong Ook ; Choi, Woo Young ; Kang, Sungho. / Integration of dual channel timing formatter system for high speed memory test equipment. ISOCC 2012 - 2012 International SoC Design Conference. 2012. pp. 185-187 (ISOCC 2012 - 2012 International SoC Design Conference).
@inproceedings{5999c2618cce409b8215c85d4ef40725,
title = "Integration of dual channel timing formatter system for high speed memory test equipment",
abstract = "This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.",
author = "Jaeseok Park and Ingeol Lee and Park, {Young Seok} and Kim, {Sung Geun} and Ryu, {Kyung Ho} and Jung, {Dong Hoon} and Kangwook Jo and Lee, {Choong Keun} and Hongil Yoon and Jung, {Seong Ook} and Choi, {Woo Young} and Sungho Kang",
year = "2012",
month = "12",
day = "1",
doi = "10.1109/ISOCC.2012.6407070",
language = "English",
isbn = "9781467329880",
series = "ISOCC 2012 - 2012 International SoC Design Conference",
pages = "185--187",
booktitle = "ISOCC 2012 - 2012 International SoC Design Conference",

}

Park, J, Lee, I, Park, YS, Kim, SG, Ryu, KH, Jung, DH, Jo, K, Lee, CK, Yoon, H, Jung, SO, Choi, WY & Kang, S 2012, Integration of dual channel timing formatter system for high speed memory test equipment. in ISOCC 2012 - 2012 International SoC Design Conference., 6407070, ISOCC 2012 - 2012 International SoC Design Conference, pp. 185-187, 2012 International SoC Design Conference, ISOCC 2012, Jeju Island, Korea, Republic of, 12/11/4. https://doi.org/10.1109/ISOCC.2012.6407070

Integration of dual channel timing formatter system for high speed memory test equipment. / Park, Jaeseok; Lee, Ingeol; Park, Young Seok; Kim, Sung Geun; Ryu, Kyung Ho; Jung, Dong Hoon; Jo, Kangwook; Lee, Choong Keun; Yoon, Hongil; Jung, Seong Ook; Choi, Woo Young; Kang, Sungho.

ISOCC 2012 - 2012 International SoC Design Conference. 2012. p. 185-187 6407070 (ISOCC 2012 - 2012 International SoC Design Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Integration of dual channel timing formatter system for high speed memory test equipment

AU - Park, Jaeseok

AU - Lee, Ingeol

AU - Park, Young Seok

AU - Kim, Sung Geun

AU - Ryu, Kyung Ho

AU - Jung, Dong Hoon

AU - Jo, Kangwook

AU - Lee, Choong Keun

AU - Yoon, Hongil

AU - Jung, Seong Ook

AU - Choi, Woo Young

AU - Kang, Sungho

PY - 2012/12/1

Y1 - 2012/12/1

N2 - This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

AB - This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

UR - http://www.scopus.com/inward/record.url?scp=84873959803&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84873959803&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2012.6407070

DO - 10.1109/ISOCC.2012.6407070

M3 - Conference contribution

AN - SCOPUS:84873959803

SN - 9781467329880

T3 - ISOCC 2012 - 2012 International SoC Design Conference

SP - 185

EP - 187

BT - ISOCC 2012 - 2012 International SoC Design Conference

ER -

Park J, Lee I, Park YS, Kim SG, Ryu KH, Jung DH et al. Integration of dual channel timing formatter system for high speed memory test equipment. In ISOCC 2012 - 2012 International SoC Design Conference. 2012. p. 185-187. 6407070. (ISOCC 2012 - 2012 International SoC Design Conference). https://doi.org/10.1109/ISOCC.2012.6407070