Integration of dual channel timing formatter system for high speed memory test equipment

Jaeseok Park, Ingeol Lee, Young Seok Park, Sung Geun Kim, Kyung Ho Ryu, Dong Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong Ook Jung, Woo Young Choi, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper proposes a dual channel timing formatter system for high speed memory test equipment. The proposed architecture supports 256 kinds of waveform with 20ps timing resolution. Moreover, timing problem is reduced because a timing generator is embedded.

Original languageEnglish
Title of host publicationISOCC 2012 - 2012 International SoC Design Conference
Pages185-187
Number of pages3
DOIs
Publication statusPublished - 2012
Event2012 International SoC Design Conference, ISOCC 2012 - Jeju Island, Korea, Republic of
Duration: 2012 Nov 42012 Nov 7

Publication series

NameISOCC 2012 - 2012 International SoC Design Conference

Other

Other2012 International SoC Design Conference, ISOCC 2012
CountryKorea, Republic of
CityJeju Island
Period12/11/412/11/7

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Integration of dual channel timing formatter system for high speed memory test equipment'. Together they form a unique fingerprint.

Cite this