Interleaving test algorithm for subthreshold leakage-current defects in DRAM considering the equal bit line stress

Hyoyoung Shin, Youngkyu Park, Gihwa Lee, Jungsik Park, Sungho Kang

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.

Original languageEnglish
Article number6514723
Pages (from-to)803-812
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number4
DOIs
Publication statusPublished - 2014 Jan 1

Fingerprint

Dynamic random access storage
Leakage currents
Defects
Random access storage
Screening
Testing

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

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abstract = "Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.",
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Interleaving test algorithm for subthreshold leakage-current defects in DRAM considering the equal bit line stress. / Shin, Hyoyoung; Park, Youngkyu; Lee, Gihwa; Park, Jungsik; Kang, Sungho.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 4, 6514723, 01.01.2014, p. 803-812.

Research output: Contribution to journalArticle

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