Abstract
Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.
| Original language | English |
|---|---|
| Article number | 6514723 |
| Pages (from-to) | 803-812 |
| Number of pages | 10 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 22 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2014 Jan 1 |
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All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
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Interleaving test algorithm for subthreshold leakage-current defects in DRAM considering the equal bit line stress. / Shin, Hyoyoung; Park, Youngkyu; Lee, Gihwa; Park, Jungsik; Kang, Sungho.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 4, 6514723, 01.01.2014, p. 803-812.Research output: Contribution to journal › Article
TY - JOUR
T1 - Interleaving test algorithm for subthreshold leakage-current defects in DRAM considering the equal bit line stress
AU - Shin, Hyoyoung
AU - Park, Youngkyu
AU - Lee, Gihwa
AU - Park, Jungsik
AU - Kang, Sungho
PY - 2014/1/1
Y1 - 2014/1/1
N2 - Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.
AB - Since the minimum feature size of dynamic RAM has been down-scaled, several studies have been carried out to determine ways to protect cell data from leakage current in many areas. In the field of testing, more appropriate test algorithms are required to detect weak cells with leakage-current sources. In this paper, we propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location. The proposed test algorithm allows screening of weak cells that cannot hold cell data due to the subthreshold leakage current. During the stress period, the algorithm can also detect other leakage currents. This paper presents the maximum stress differences according to the cell location, and determines the influence of the refresh operation on the maximum stress time. Therefore, this paper suggests a correlation between the refresh and read time to give maximum stress time.
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UR - http://www.scopus.com/inward/citedby.url?scp=84897446042&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2013.2255628
DO - 10.1109/TVLSI.2013.2255628
M3 - Article
VL - 22
SP - 803
EP - 812
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 4
M1 - 6514723
ER -