High bit-density flash memories such as Multi-Level Cell (MLC) and Triple-Level Cell (TLC) flash have become a norm, since doubling the cell bit-density can increase the storage capacity by 2X using the same number of cells. However, these high bit-density flash memories suffer from the read variation problem-e.g., the three kinds of bits (i.e., lower, middle, and upper bits) in a TLC cell have different read latencies; reading an upper bit takes a longer time than reading a middle bit, and reading a lower bit takes the minimum time. In this paper, we note that, in the conventional coding, the long read latencies of the middle and upper bits are not reduced even after the lower bit value is invalidated (i.e., no longer used). Motivated by this problem with the traditional coding, we propose a new coding technique, called Invalid Data-Aware (IDA) coding, which reduces the upper and middle bit read latencies close to the lower bit read latency when the lower bit becomes invalid. The main strategy the IDA coding employs is to merge the duplicated voltage states coming from the bit invalidation and reduce the number of (read) trials to identify the voltage state of a cell. To hide the performance and reliability degradation caused by the application of the IDA coding, we also propose to implement it as a part of the data refresh function, which is a fundamental operation in modern SSDs to keep its data safer and longer. With an extensive analysis of a TLC-based SSD using a variety of read-intensive workloads, we report that our IDA coding improves the read response times by 28%, on average; it is also quite effective in devices with different bit densities and timing parameters.
|Title of host publication||Proceedings - 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018|
|Publisher||IEEE Computer Society|
|Number of pages||12|
|Publication status||Published - 2018 Dec 12|
|Event||51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018 - Fukuoka, Japan|
Duration: 2018 Oct 20 → 2018 Oct 24
|Name||Proceedings of the Annual International Symposium on Microarchitecture, MICRO|
|Other||51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018|
|Period||18/10/20 → 18/10/24|
Bibliographical noteFunding Information:
ACKNOWLEDGEMENTS This work is supported in part by NSF grants 1822923, 1439021, 1629915, 1626251, 1629129, 1763681, 1526750 and 1439057. Jung’s research is in part supported by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231,IITP-2018-2017-0-01015, NRF 2015M3C4A7065645, Yonsei Future Research Grant (2017-22-0105), and a grant from MemRay. M. Jung and M. Kandemir are the co-corresponding authors.
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture