The proposed scheme, called the IOC-LP (input reduction and one block compression for low power test), compresses the test data of scan based SoCs to improve the compression ratio in the ATPG process. It does so by using the modified input reduction and novel techniques, a new scan flip-flop reordering for low power test, the newly proposed one block compression, and a novel reordering algorithm. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is able to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed method leads to a better compression ratio with lower hardware overhead and lower power consumption than previous works. Experimental results on ISCAS '89 and ITC '99 benchmark circuits validated the proposed method.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering