Jitter-conscious bus arbitration scheme for real-time systems

Jong Ho Roh, Minje Jun, Kwanhu Bang, Eui Young Chung

Research output: Contribution to journalArticlepeer-review


Jitter is the variation of latencies, when real-time Intellectual Properties (IPs) are accessing data from the data storages. It is a critical factor for such IPs from the Quality-of-Service (QoS) perspective. Jitter of a real-time IP can be measured by how frequently it experiences the underflows and overflows from its data queue in read mode and write mode, respectively. Such failures critically depend on the bus arbitration scheme which determines the bus acquisition order of IPs. The proposed idea allows IPs to inform the bus arbiter of the status of their data buffers when they assert bus requests. Such information helps the bus arbiter to determine the bus acquisition order while greatly reducing the jitter. The experimental results show that our method effectively eliminates the over-flows and underflows of real-time IPs by dynamically preempting the jitter-critical bus requests.

Original languageEnglish
Pages (from-to)643-647
Number of pages5
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number2
Publication statusPublished - 2009 Feb

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


Dive into the research topics of 'Jitter-conscious bus arbitration scheme for real-time systems'. Together they form a unique fingerprint.

Cite this