This paper presents designs and measurements of K a-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-μm CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at 35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and > 32-dB isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (IP1 dB) can be significantly increased to ∼ 23 dBm with the use of a high substrate resistance design. In contrast, IP1 dB of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13-μm CMOS designs can be used for state-of-the-art switches at 26-40 GHz.
|Number of pages||8|
|Journal||IEEE Transactions on Microwave Theory and Techniques|
|Publication status||Published - 2008 Jun|
Bibliographical noteFunding Information:
Manuscript received December 6, 2007; revised March 3, 2008. This work was supported by the U.S. Army Research Laboratories under a Collaborative Technology Agreement (CTA).
The authors thank A. Hung and E. Viveiros, both with the U.S. Army Research Laboratories, Adelphi, MD, for supporting this research under the Collaborative Technology Agreement (CTA) effort.
All Science Journal Classification (ASJC) codes
- Condensed Matter Physics
- Electrical and Electronic Engineering