Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance

Byung Wook Min, Gabriel M. Rebeiz

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper presents 35 GHz single-pole-singlethrow (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 μm BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.

Original languageEnglish
Title of host publicationProceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
Pages569-572
Number of pages4
DOIs
Publication statusPublished - 2007 Oct 2
Event2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 - Honolulu, HI, United States
Duration: 2007 Jun 32007 Jun 5

Other

Other2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
CountryUnited States
CityHonolulu, HI
Period07/6/307/6/5

Fingerprint

Poles
Switches
Substrates
Insertion losses
Frequency bands
Transistors
Demonstrations

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Min, B. W., & Rebeiz, G. M. (2007). Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. In Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 (pp. 569-572). [4266496] https://doi.org/10.1109/RFIC.2007.380948
Min, Byung Wook ; Rebeiz, Gabriel M. / Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. pp. 569-572
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Min, BW & Rebeiz, GM 2007, Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. in Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007., 4266496, pp. 569-572, 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007, Honolulu, HI, United States, 07/6/3. https://doi.org/10.1109/RFIC.2007.380948

Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. / Min, Byung Wook; Rebeiz, Gabriel M.

Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. p. 569-572 4266496.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - This paper presents 35 GHz single-pole-singlethrow (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 μm BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.

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Min BW, Rebeiz GM. Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. In Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. p. 569-572. 4266496 https://doi.org/10.1109/RFIC.2007.380948