LARECD: Low area overhead and reliable error correction DMR architecture

Hyunyul Lim, Taehyun Kim, Dongsu Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Recent HPC system generally is composed of enormous amounts of GPUs. GPU-based HPC system makes a reliability problem from the absence of error detection unit in GPUs. For improving the reliability of GPU, dual modular redundancy(DMR) architecture is presented. However, current DMR architectures do not care much to the correction sequence. Therefore, the data hazard can occur during the recovery sequence. We present LARECD (Low Area overhead and Reliable Error Correction DMR) architecture. This architecture can secure the error correction sequence from the data hazard. Experimental result demonstrates the efficiency of LARECD architecture.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages27-28
Number of pages2
ISBN (Electronic)9781538622858
DOIs
Publication statusPublished - 2018 May 29
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 2017 Nov 52017 Nov 8

Publication series

NameProceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other14th International SoC Design Conference, ISOCC 2017
CountryKorea, Republic of
CitySeoul
Period17/11/517/11/8

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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