Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates

Ajjiporn Dathbun, Youngchan Kim, Seongchan Kim, Youngjae Yoo, Moon Sung Kang, Changgu Lee, Jeong Ho Cho

Research output: Contribution to journalArticlepeer-review

32 Citations (Scopus)

Abstract

We demonstrated the fabrication of large-area ReS2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS2 transistors with graphene electrodes decreased dramatically compared with the SiO2-devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm2/(V s) and an on/off current ratio exceeding 104. NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Original languageEnglish
Pages (from-to)2999-3005
Number of pages7
JournalNano letters
Volume17
Issue number5
DOIs
Publication statusPublished - 2017 May 10

All Science Journal Classification (ASJC) codes

  • Bioengineering
  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics
  • Mechanical Engineering

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