Large-Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

Seongchan Kim, Young Jin Choi, Yongsuk Choi, Moon Sung Kang, Jeong Ho Cho

Research output: Contribution to journalArticle

14 Citations (Scopus)

Abstract

The fabrication of all-transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution-processed indium-gallium-zinc-oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm−2) and on–off current ratios (>104) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low-power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large-area, and room-temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene-based future electronics.

Original languageEnglish
Article number1700651
JournalAdvanced Functional Materials
Volume27
Issue number30
DOIs
Publication statusPublished - 2017 Aug 11

Fingerprint

Graphite
Oxides
Graphene
Heterojunctions
Transistors
transistors
Gels
Logic gates
Gate dielectrics
Ions
oxides
Zinc Oxide
Fabrication
Gallium
Electrodes
Indium
Electric potential
Zinc oxide
graphene
gels

All Science Journal Classification (ASJC) codes

  • Chemistry(all)
  • Materials Science(all)
  • Condensed Matter Physics

Cite this

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title = "Large-Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures",
abstract = "The fabrication of all-transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution-processed indium-gallium-zinc-oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm−2) and on–off current ratios (>104) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low-power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large-area, and room-temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene-based future electronics.",
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Large-Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures. / Kim, Seongchan; Choi, Young Jin; Choi, Yongsuk; Kang, Moon Sung; Cho, Jeong Ho.

In: Advanced Functional Materials, Vol. 27, No. 30, 1700651, 11.08.2017.

Research output: Contribution to journalArticle

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AB - The fabrication of all-transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution-processed indium-gallium-zinc-oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm−2) and on–off current ratios (>104) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low-power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large-area, and room-temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene-based future electronics.

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