TY - JOUR
T1 - Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM
AU - Song, Byungkyu
AU - Na, Taehui
AU - Kim, Jisu
AU - Kim, Jung Pill
AU - Kang, Seung H.
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 2015 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2015/7/1
Y1 - 2015/7/1
N2 - As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2\times faster sensing speed, 1.12\times lower read energy, and 1.13\times smaller area when compared with the best value of design parameters of other sense amplifiers.
AB - As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2\times faster sensing speed, 1.12\times lower read energy, and 1.13\times smaller area when compared with the best value of design parameters of other sense amplifiers.
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U2 - 10.1109/TCSI.2015.2427931
DO - 10.1109/TCSI.2015.2427931
M3 - Article
AN - SCOPUS:85027953700
VL - 62
SP - 1776
EP - 1784
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 7
M1 - 7128422
ER -