As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2\times faster sensing speed, 1.12\times lower read energy, and 1.13\times smaller area when compared with the best value of design parameters of other sense amplifiers.
|Number of pages||9|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 2015 Jul 1|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering