Level-converting retention flip-flop for reducing standby power in ZigBee SoCs

Jung Hyun Park, Heechai Kang, Dong Hoon Jung, Kyungho Ryu, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)


In this paper, we propose a level-converting retention flip-flop (RFF) for ZigBee systems-on-chips (SoCs). The proposed RFF allows the voltage regulator that generates the core supply voltage (VDD,core) to be turned off in the standby mode, and it thus reduces the standby power of the ZigBee SoCs. The logic states are retained in a slave latch composed of thick-oxide transistors using an I/O supply voltage (VDD,IO) that is always turned on. Level-up conversion from VDD is achieved by an embedded nMOS pass-transistor level-conversion scheme that uses a low-only signal-transmitting technique. By embedding a retention latch and level-up converter into the data-to-output path of the proposed RFF, the RFF resolves the problems of the static RAM-based RFF, such as large dc current and low readability caused by threshold drop. The proposed RFF does not also require additional control signals for power mode transitioning. Using 0.13- μm process technology, we implemented an RFF with VDD,core and VDD,IO of 1.2 and 2.5 V, respectively. The maximum operating frequency is 300 MHz. The active energy of the RFF is 191.70 fJ, and its standby power is 350.25 pW.

Original languageEnglish
Article number6781586
Pages (from-to)413-421
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
Publication statusPublished - 2015 Mar 1

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'Level-converting retention flip-flop for reducing standby power in ZigBee SoCs'. Together they form a unique fingerprint.

Cite this