PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can significantly degrade system performance. In this paper, we analyze a PCM implementation in depth, and identify the primary cause of PCM's long latency, i.e., a long interconnect (high resistance/capacitance) path between a cell and a sense-amp/writedriver. This in turn requires (1) a very large charge pump consuming: ∼20% of PCM chip space, ∼50% of latency of write operations, and ∼2× more power than a write operation itself; and (2) a large current sense-amp with long time to pre-charge the interconnect path. Then, we propose Low-Latency PCM (LLPCM) architecture. Our analysis shows that LL-PCM can give 119% higher performance and consume 43% lower memory energy than PCM for memory-intensive applications. LL-PCM is only ∼1% larger than PCM, as the cost of reducing the resistance/capacitance of the interconnect path is negated by its 4.1× smaller charge pump.
|Title of host publication||Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2019 Jun 2|
|Event||56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States|
Duration: 2019 Jun 2 → 2019 Jun 6
|Name||Proceedings - Design Automation Conference|
|Conference||56th Annual Design Automation Conference, DAC 2019|
|Period||19/6/2 → 19/6/6|
Bibliographical noteFunding Information:
This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317. This work was completed when Nam Sung Kim was at the University of Illinois, Urbana-Champaign.
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modelling and Simulation