In this brief, a local bit-line (LBL) SRAM with data-aware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of 5.12σ, write ability yield of 7.26σ, and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2023 Jan 1|
Bibliographical noteFunding Information:
This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (MSIT) under Grant 2021R1A2C2008297.
© 2004-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering