Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist

Tae Woo Oh; Juhyun Park; Tae Hyun Kim; Keonhee Cho; Seong Ook Jung

doi:10.1109/TCSII.2022.3206478

Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist

Tae Woo Oh, Juhyun Park, Tae Hyun Kim, Keonhee Cho, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

In this brief, a local bit-line (LBL) SRAM with data-aware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of 5.12σ, write ability yield of 7.26σ, and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.

Original language	English
Pages (from-to)	306-310
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	70
Issue number	1
DOIs	https://doi.org/10.1109/TCSII.2022.3206478
Publication status	Published - 2023 Jan 1

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (MSIT) under Grant 2021R1A2C2008297.

Publisher Copyright:
© 2004-2012 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/TCSII.2022.3206478

Cite this

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title = "Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist",

abstract = "In this brief, a local bit-line (LBL) SRAM with data-aware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of 5.12σ, write ability yield of 7.26σ, and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.",

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AU - Kim, Tae Hyun

AU - Cho, Keonhee

AU - Jung, Seong Ook

N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea Government (MSIT) under Grant 2021R1A2C2008297. Publisher Copyright: © 2004-2012 IEEE.

PY - 2023/1/1

Y1 - 2023/1/1

N2 - In this brief, a local bit-line (LBL) SRAM with data-aware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of 5.12σ, write ability yield of 7.26σ, and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.

AB - In this brief, a local bit-line (LBL) SRAM with data-aware power-gating write assist is proposed for near-threshold operation. The proposed SRAM achieves high read stability and write ability by adopting LBL architecture and power-gating transistors, respectively. Depending on the input data, one of the power-gating transistors is adaptively cut off, which eliminates the write disturbance from the power supply. Thus, reliable write operation can be performed. The proposed SRAM achieves a read stability yield of 5.12σ, write ability yield of 7.26σ, and consumes 0.21 pJ energy/operation with 58% shorter read delay and 33% smaller area per bit than the 12T SRAM at a supply voltage of 0.4 V in a 22-nm FinFET process.

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Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist

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