Silicon nanowires (Si NWs) showing stabilized n-type conductivity, which can be fabricated with high yield by simple surface treatment, are presented in this study. Si NWs were initially fabricated by electroless etching of phosphine-doped n-type Si wafers. At this stage, Si NWs showed large scatter in electrical properties. Once these nanowires were post-annealed in oxidizing ambient and then wet-etched in dilute HF solution, their electrical properties were markedly improved and stabilized to show proper n-type conductivity. Microstructural examination revealed that such improvements and stabilization accompanied flattening of the outer surface and removal of surface defects due to the surface treatment processes. To demonstrate the applicability of these n-type Si NWs to logic devices, a model complementary metal-oxide-semiconductor (CMOS) was prepared by transfer implantation of p- and n-type Si NWs on a poly(4-vinylphenol) layer and this model CMOS showed logic inverter characteristic with controllable gain.
All Science Journal Classification (ASJC) codes
- Materials Chemistry