Long single ZnO nanowire for logic and memory circuits: NOT, NAND, NOR gate, and SRAM

Young Tack Lee, Syed Raza Ali Raza, Pyo Jin Jeon, Ryong Ha, Heon Jin Choi, Seongil Im

Research output: Contribution to journalArticle

21 Citations (Scopus)


We demonstrate logic and static random access memory (SRAM) circuits using a 100 μm long and 100 nm thin single ZnO nanowire (NW), which acts as a channel of field-effect transistors (FETs) with Al2O3 dielectrics. NW FETs are thus arrayed in one dimension to consist of NOT, NAND, and NOR gate logic, and SRAM circuits. Two respective top-gate NW FETs with Au and indium-tin-oxide (ITO) were connected to form an inverter, the basic NOT gate component, since the former gate leads to an enhanced mode FET while the latter to depletion mode due to their work function difference. Our inverters showed a high voltage gain of 22 under a 5 V operational voltage, resulting in successful operation of all other devices. We thus conclude that our long single NW approach is quite promising to extend the field of nano-electronics.

Original languageEnglish
Pages (from-to)4181-4185
Number of pages5
Issue number10
Publication statusPublished - 2013 May 21


All Science Journal Classification (ASJC) codes

  • Materials Science(all)

Cite this