Abstract
A new low-complexity architecture CDMA rake receiver for multi-code CDMA systems is proposed. It contains shared hardware blocks to reduce hardware complexity. The hardware complexity of the proposed architecture is compared with that of a conventional CDMA rake receiver in terms of the number of Walsh code channels. The result shows that our proposed architecture has a 12 and 18.6% reduction in gate count when the number of Walsh code channels is 4 and 7, respectively.
| Original language | English |
|---|---|
| Pages (from-to) | 1382-1383 |
| Number of pages | 2 |
| Journal | Electronics Letters |
| Volume | 34 |
| Issue number | 14 |
| DOIs | |
| Publication status | Published - 1998 Jul 9 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
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Low-complexity architecture of rake receiver for multi-code CDMA system. / Lee, Seongjoo; Hwang, Sangyun; Kim, Jaeseok.
In: Electronics Letters, Vol. 34, No. 14, 09.07.1998, p. 1382-1383.Research output: Contribution to journal › Article
TY - JOUR
T1 - Low-complexity architecture of rake receiver for multi-code CDMA system
AU - Lee, Seongjoo
AU - Hwang, Sangyun
AU - Kim, Jaeseok
PY - 1998/7/9
Y1 - 1998/7/9
N2 - A new low-complexity architecture CDMA rake receiver for multi-code CDMA systems is proposed. It contains shared hardware blocks to reduce hardware complexity. The hardware complexity of the proposed architecture is compared with that of a conventional CDMA rake receiver in terms of the number of Walsh code channels. The result shows that our proposed architecture has a 12 and 18.6% reduction in gate count when the number of Walsh code channels is 4 and 7, respectively.
AB - A new low-complexity architecture CDMA rake receiver for multi-code CDMA systems is proposed. It contains shared hardware blocks to reduce hardware complexity. The hardware complexity of the proposed architecture is compared with that of a conventional CDMA rake receiver in terms of the number of Walsh code channels. The result shows that our proposed architecture has a 12 and 18.6% reduction in gate count when the number of Walsh code channels is 4 and 7, respectively.
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U2 - 10.1049/el:19980990
DO - 10.1049/el:19980990
M3 - Article
VL - 34
SP - 1382
EP - 1383
JO - Electronics Letters
JF - Electronics Letters
SN - 0013-5194
IS - 14
ER -