This paper proposes a cyclic shift decomposition (CSD) algorithm to perform multi-way cyclic shifts with low complexity in the quasi-cyclic low-density parity-check (QCLDPC) decoder. The proposed algorithm decomposes the cyclic shift into a common cyclic shift and a private cyclic shift. Based on the proposed CSD algorithm, a low-complexity multi-way and reconfigurable cyclic shift network (CSN) for QC-LDPC codes is proposed. The proposed CSN is composed of the shared component, which performs the common cyclic shift, and the repeated component, which performs the private cyclic shift. Each component can support reconfigurability for given QCLDPC codes. By introducing the single-path shared component, only the complexity of the multi-path repeated component increases linearly as the number of multi-way paths increases. A complexity analysis of each component is also proposed. Based on the complexity analysis, the proposed CSN can perform multi-way and reconfigurable cyclic shifts with low complexity in the QC-LDPC decoder. The implementation results show that the areas of the proposed four-way CSN are 0.227 mm2 and 0.276 mm2 for the IEEE 802.11n/ac and IEEE 802.16e QC-LDPC codes, respectively, with 130 nm CMOS technology. The area saving per each-way is from 13.8% to 86.5% compared with previously presented works.
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering