In this brief, a low-complexity hardware architecture for multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) symbol detectors with two transmit and two receive antennas is proposed. The detectors support two MIMO-OFDM schemes of space–frequency block coded OFDM and space-division multiplexing OFDM in order to achieve higher performance and throughput However, symbol detection processes for these two schemes have high computational complexity, which is a burden to hardware implementation of MIMO-OFDM symbol detectors. In order to reduce complexity, the proposed symbol detector is designed with shared architecture, where similar functional blocks are merged and share the hardware resources, and results in the reduction of logic gates by 34% over a conventional architecture employing two individual detectors.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2006 Dec|
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering