Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

Seung Moon Yoo, Seong Ook Jung, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, a new test pattern generator with a 2-level LFSR and a fast pattern transferring method for the scan-based BIST structure are proposed. XOR input paths in the 2-level LFSR scheme are changed by counter outputs to generate less linear-dependent and auto-correlated test patterns for better fault coverage. Test patterns are transferred into the scan chain by using an asynchronous internal high frequency clock to reduce test time.

Original languageEnglish
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages1-4
Number of pages4
DOIs
Publication statusPublished - 2001 Dec 1
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: 2001 May 62001 May 9

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period01/5/601/5/9

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Yoo, S. M., Jung, S. O., & Kang, S. M. (2001). Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 1-4). [922153] (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922153