Low cost endurance test-pattern generation for multi-level cell flash memory

Jaewon Cha, Keewon Cho, Seunggeon Yu, Sungho Kang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

Original languageEnglish
Pages (from-to)147-155
Number of pages9
JournalJournal of Semiconductor Technology and Science
Volume17
Issue number1
DOIs
Publication statusPublished - 2017 Feb 1

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Flash memory
Durability
Testing
Costs
Experiments

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

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Low cost endurance test-pattern generation for multi-level cell flash memory. / Cha, Jaewon; Cho, Keewon; Yu, Seunggeon; Kang, Sungho.

In: Journal of Semiconductor Technology and Science, Vol. 17, No. 1, 01.02.2017, p. 147-155.

Research output: Contribution to journalArticle

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