Abstract
Lattice reduction (LR) techniques have been widely adopted to enhance the detection performance with low additional complexity in spatial multiplexed multiple-input multiple-output (MIMO) systems. However, in large MIMO systems, the required number of iterations and the corresponding latency and complexity of the existing LR algorithms increase exponentially. In this brief, we propose a low-latency LR method based on Seysen's algorithm (SA) for high-dimensional MIMO systems. The proposed algorithm introduces dual-index selection and simultaneously updates two basis pairs without the recalculation of metrics to reduce the latency and complexity. Additionally, it introduces a reduced candidate set to decrease the computational complexity and memory usage. The numerical results demonstrate that the proposed LR-aided linear detector outperforms the conventional Lenstra-Lenstra-Lovász algorithm. Furthermore, the performance of the proposed method is comparable to that of SA; it achieves reductions of 40% and 12.5% in the number of iterations and computational complexity, respectively. The proposed 65-nm CMOS implementation achieves an overall latency of 196 ns and a throughput of 25.5 M matrix/s with a clock frequency of 357.1 MHz for $8 \times 8$ MIMO systems.
Original language | English |
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Article number | 9051976 |
Pages (from-to) | 2993-2997 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 67 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2020 Dec |
Bibliographical note
Funding Information:Manuscript received February 23, 2020; accepted March 24, 2020. Date of publication March 31, 2020; date of current version November 24, 2020. This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIP) under Grant NRF-2015R1A2A2A01004883, and in part by the System LSI Division of Samsung Electronics Company Ltd. This brief was recommended by Associate Editor Q. Liu. (Corresponding author: Jaeseok Kim.) The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 03722, South Korea (e-mail: jaekim@yonsei.ac.kr). Digital Object Identifier 10.1109/TCSII.2020.2984325
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© 2004-2012 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering