Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal-oxide semiconductor technology

Jin Sung Youn, Myung Jae Lee, Kang Yeob Park, Wang Soo Kim, Woo Young Choi

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

The authors present a low-power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal-oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low-power operation. Their OEIC receiver consists of a CMOS-compatible avalanche photodetector and electronic circuits that include an inverter-based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit-error rate <10-12 at incident optical power of -4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers.

Original languageEnglish
Pages (from-to)221-226
Number of pages6
JournalIET Circuits, Devices and Systems
Volume9
Issue number3
DOIs
Publication statusPublished - 2015 May 1

Fingerprint

Integrated optoelectronics
Metals
Operational amplifiers
Equalizers
Photodetectors
Oxide semiconductors
Bit error rate
Energy efficiency
Electric power utilization
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

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abstract = "The authors present a low-power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal-oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low-power operation. Their OEIC receiver consists of a CMOS-compatible avalanche photodetector and electronic circuits that include an inverter-based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit-error rate <10-12 at incident optical power of -4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers.",
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Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal-oxide semiconductor technology. / Youn, Jin Sung; Lee, Myung Jae; Park, Kang Yeob; Kim, Wang Soo; Choi, Woo Young.

In: IET Circuits, Devices and Systems, Vol. 9, No. 3, 01.05.2015, p. 221-226.

Research output: Contribution to journalArticle

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