Low-power data cache architecture by address range reconfiguration for multimedia applications

Hoon Mo Yang, Gi Ho Park, Shin-Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Today's portable electric consumer devices tend to include more multimedia processing capabilities. This trend results increased processing resources, thus causing more power consumption. Therefore, the power-efficiency becomes important due to battery operated nature of portable devices. In this paper, we propose a reconfigurable data cache architecture, in which data allocation to a cache is constrained by address range configuration. Then we evaluate trade-off between performance and power efficiency. Comparing to the conventional cache architectures, power consumption can be reduced decently while maintaining miss rate of the proposed data cache similar to those of the conventional caches. The result shows that the reconfigurable data cache operates with 33.2%, 53.3%, and 70.4% less power when compared with direct-mapped, 2-way, and 4-way set-associative caches respectively.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
Pages574-580
Number of pages7
Publication statusPublished - 2006 Dec 8
Event11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006 - Shanghai, China
Duration: 2006 Sep 62006 Sep 8

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4186 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006
CountryChina
CityShanghai
Period06/9/606/9/8

Fingerprint

Multimedia Applications
Reconfiguration
Cache
Electric power utilization
Processing
Range of data
Power Consumption
Data Allocation
Architecture
Battery
Multimedia
Trade-offs
Tend
Configuration
Resources
Evaluate

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Yang, H. M., Park, G. H., & Kim, S-D. (2006). Low-power data cache architecture by address range reconfiguration for multimedia applications. In Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings (pp. 574-580). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4186 LNCS).
Yang, Hoon Mo ; Park, Gi Ho ; Kim, Shin-Dug. / Low-power data cache architecture by address range reconfiguration for multimedia applications. Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. 2006. pp. 574-580 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
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abstract = "Today's portable electric consumer devices tend to include more multimedia processing capabilities. This trend results increased processing resources, thus causing more power consumption. Therefore, the power-efficiency becomes important due to battery operated nature of portable devices. In this paper, we propose a reconfigurable data cache architecture, in which data allocation to a cache is constrained by address range configuration. Then we evaluate trade-off between performance and power efficiency. Comparing to the conventional cache architectures, power consumption can be reduced decently while maintaining miss rate of the proposed data cache similar to those of the conventional caches. The result shows that the reconfigurable data cache operates with 33.2{\%}, 53.3{\%}, and 70.4{\%} less power when compared with direct-mapped, 2-way, and 4-way set-associative caches respectively.",
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Yang, HM, Park, GH & Kim, S-D 2006, Low-power data cache architecture by address range reconfiguration for multimedia applications. in Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4186 LNCS, pp. 574-580, 11th Asia-Pacific Conference on Advances in Computer Systems Architecture, ACSAC 2006, Shanghai, China, 06/9/6.

Low-power data cache architecture by address range reconfiguration for multimedia applications. / Yang, Hoon Mo; Park, Gi Ho; Kim, Shin-Dug.

Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. 2006. p. 574-580 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4186 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Yang HM, Park GH, Kim S-D. Low-power data cache architecture by address range reconfiguration for multimedia applications. In Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. 2006. p. 574-580. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).