The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and the test power consumption. The proposed technique can reduce both test data volume and power consumption with the minimal impact on area overhead. Unused segments, which consist of don't care bits, can be bypassed in the proposed scan bypass technique. In order to maximize the bypassing portion, scan cell ordering and pattern ordering are performed. Experimental results show that the proposed technique efficiently reduce test power and test data volume with a small overhead.
|Title of host publication||Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015|
|Publisher||IEEE Computer Society|
|Number of pages||4|
|Publication status||Published - 2015 Apr 13|
|Event||16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States|
Duration: 2015 Mar 2 → 2015 Mar 4
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Other||16th International Symposium on Quality Electronic Design, ISQED 2015|
|Period||15/3/2 → 15/3/4|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality