Low power scan bypass technique with test data reduction

Hyunyul Lim, Wooheon Kang, Sungyoul Seo, Yong Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and the test power consumption. The proposed technique can reduce both test data volume and power consumption with the minimal impact on area overhead. Unused segments, which consist of don't care bits, can be bypassed in the proposed scan bypass technique. In order to maximize the bypassing portion, scan cell ordering and pattern ordering are performed. Experimental results show that the proposed technique efficiently reduce test power and test data volume with a small overhead.

Original languageEnglish
Title of host publicationProceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PublisherIEEE Computer Society
Pages173-176
Number of pages4
Volume2015-April
ISBN (Electronic)9781479975815
DOIs
Publication statusPublished - 2015 Jan 1
Event16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
Duration: 2015 Mar 22015 Mar 4

Other

Other16th International Symposium on Quality Electronic Design, ISQED 2015
CountryUnited States
CitySanta Clara
Period15/3/215/3/4

Fingerprint

Data reduction
Electric power utilization
Semiconductor materials

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Lim, H., Kang, W., Seo, S., Lee, Y., & Kang, S. (2015). Low power scan bypass technique with test data reduction. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015 (Vol. 2015-April, pp. 173-176). [7085419] IEEE Computer Society. https://doi.org/10.1109/ISQED.2015.7085419
Lim, Hyunyul ; Kang, Wooheon ; Seo, Sungyoul ; Lee, Yong ; Kang, Sungho. / Low power scan bypass technique with test data reduction. Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. Vol. 2015-April IEEE Computer Society, 2015. pp. 173-176
@inproceedings{c1af6779b8ca4a0893ec76039eab2343,
title = "Low power scan bypass technique with test data reduction",
abstract = "The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and the test power consumption. The proposed technique can reduce both test data volume and power consumption with the minimal impact on area overhead. Unused segments, which consist of don't care bits, can be bypassed in the proposed scan bypass technique. In order to maximize the bypassing portion, scan cell ordering and pattern ordering are performed. Experimental results show that the proposed technique efficiently reduce test power and test data volume with a small overhead.",
author = "Hyunyul Lim and Wooheon Kang and Sungyoul Seo and Yong Lee and Sungho Kang",
year = "2015",
month = "1",
day = "1",
doi = "10.1109/ISQED.2015.7085419",
language = "English",
volume = "2015-April",
pages = "173--176",
booktitle = "Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015",
publisher = "IEEE Computer Society",
address = "United States",

}

Lim, H, Kang, W, Seo, S, Lee, Y & Kang, S 2015, Low power scan bypass technique with test data reduction. in Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. vol. 2015-April, 7085419, IEEE Computer Society, pp. 173-176, 16th International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, United States, 15/3/2. https://doi.org/10.1109/ISQED.2015.7085419

Low power scan bypass technique with test data reduction. / Lim, Hyunyul; Kang, Wooheon; Seo, Sungyoul; Lee, Yong; Kang, Sungho.

Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. Vol. 2015-April IEEE Computer Society, 2015. p. 173-176 7085419.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Low power scan bypass technique with test data reduction

AU - Lim, Hyunyul

AU - Kang, Wooheon

AU - Seo, Sungyoul

AU - Lee, Yong

AU - Kang, Sungho

PY - 2015/1/1

Y1 - 2015/1/1

N2 - The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and the test power consumption. The proposed technique can reduce both test data volume and power consumption with the minimal impact on area overhead. Unused segments, which consist of don't care bits, can be bypassed in the proposed scan bypass technique. In order to maximize the bypassing portion, scan cell ordering and pattern ordering are performed. Experimental results show that the proposed technique efficiently reduce test power and test data volume with a small overhead.

AB - The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and the test power consumption. The proposed technique can reduce both test data volume and power consumption with the minimal impact on area overhead. Unused segments, which consist of don't care bits, can be bypassed in the proposed scan bypass technique. In order to maximize the bypassing portion, scan cell ordering and pattern ordering are performed. Experimental results show that the proposed technique efficiently reduce test power and test data volume with a small overhead.

UR - http://www.scopus.com/inward/record.url?scp=84944317266&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84944317266&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2015.7085419

DO - 10.1109/ISQED.2015.7085419

M3 - Conference contribution

VL - 2015-April

SP - 173

EP - 176

BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015

PB - IEEE Computer Society

ER -

Lim H, Kang W, Seo S, Lee Y, Kang S. Low power scan bypass technique with test data reduction. In Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015. Vol. 2015-April. IEEE Computer Society. 2015. p. 173-176. 7085419 https://doi.org/10.1109/ISQED.2015.7085419