Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.
|Title of host publication||Proceedings - International SoC Design Conference 2018, ISOCC 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2019 Feb 22|
|Event||15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of|
Duration: 2018 Nov 12 → 2018 Nov 15
|Name||Proceedings - International SoC Design Conference 2018, ISOCC 2018|
|Conference||15th International SoC Design Conference, ISOCC 2018|
|Country||Korea, Republic of|
|Period||18/11/12 → 18/11/15|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].
© 2018 IEEE.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials