Low Power Scan Chain Architecture Based on Circuit Topology

Heetae Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2018, ISOCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages267-268
Number of pages2
ISBN (Electronic)9781538679609
DOIs
Publication statusPublished - 2019 Feb 22
Event15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of
Duration: 2018 Nov 122018 Nov 15

Publication series

NameProceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference15th International SoC Design Conference, ISOCC 2018
CountryKorea, Republic of
CityDaegu
Period18/11/1218/11/15

Fingerprint

Electric network topology
Electric power utilization
Controllability
Digital circuits
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Kim, H., Oh, H., Lee, S., & Kang, S. (2019). Low Power Scan Chain Architecture Based on Circuit Topology. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 267-268). [8649956] (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649956
Kim, Heetae ; Oh, Hyunggoy ; Lee, Sangjun ; Kang, Sungho. / Low Power Scan Chain Architecture Based on Circuit Topology. Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 267-268 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).
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Kim, H, Oh, H, Lee, S & Kang, S 2019, Low Power Scan Chain Architecture Based on Circuit Topology. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649956, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 267-268, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649956

Low Power Scan Chain Architecture Based on Circuit Topology. / Kim, Heetae; Oh, Hyunggoy; Lee, Sangjun; Kang, Sungho.

Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 267-268 8649956 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.

AB - Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.

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Kim H, Oh H, Lee S, Kang S. Low Power Scan Chain Architecture Based on Circuit Topology. In Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 267-268. 8649956. (Proceedings - International SoC Design Conference 2018, ISOCC 2018). https://doi.org/10.1109/ISOCC.2018.8649956