Low power SRAM design for 14 nm GAA Si-nanowire technology

Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, Seongook Jung

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This paper presents a low power and stable 6-T nanowire SRAM cell design by tuning the extension length of the access transistor. Our approach significantly reduces the power dissipation with a low active area and improves the SRAM cell read stability. We utilize device design parameters such as the nanowire diameter, the number of nanowires, and the device extension length to improve the stability of the SRAM cells. We find that the extension length tuning technique exhibits 15% and ∼60% savings in active area and static power consumption, respectively, in comparison to a conventional multi-nanowire tuning technique. In addition, the proposed technique achieves 6% and 8% improvements in the read and hold noise margins, respectively, with a 6.5% decrease in write noise margin and a ∼14% increase in the read/write access time. Our results show that the extension length-tuned access transistor is an excellent option for improving the satiability with low power for sub-14-nm technologies.

Original languageEnglish
Pages (from-to)1239-1247
Number of pages9
JournalMicroelectronics Journal
Volume46
Issue number12
DOIs
Publication statusPublished - 2015 Dec 1

Fingerprint

Static random access storage
Nanowires
nanowires
Tuning
tuning
margins
Transistors
transistors
cells
access time
Energy dissipation
Electric power utilization
dissipation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Kaushal, G., Jeong, H., Maheshwaram, S., Manhas, S. K., Dasgupta, S., & Jung, S. (2015). Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectronics Journal, 46(12), 1239-1247. https://doi.org/10.1016/j.mejo.2015.10.016
Kaushal, Gaurav ; Jeong, H. ; Maheshwaram, Satish ; Manhas, S. K. ; Dasgupta, S. ; Jung, Seongook. / Low power SRAM design for 14 nm GAA Si-nanowire technology. In: Microelectronics Journal. 2015 ; Vol. 46, No. 12. pp. 1239-1247.
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Kaushal, G, Jeong, H, Maheshwaram, S, Manhas, SK, Dasgupta, S & Jung, S 2015, 'Low power SRAM design for 14 nm GAA Si-nanowire technology', Microelectronics Journal, vol. 46, no. 12, pp. 1239-1247. https://doi.org/10.1016/j.mejo.2015.10.016

Low power SRAM design for 14 nm GAA Si-nanowire technology. / Kaushal, Gaurav; Jeong, H.; Maheshwaram, Satish; Manhas, S. K.; Dasgupta, S.; Jung, Seongook.

In: Microelectronics Journal, Vol. 46, No. 12, 01.12.2015, p. 1239-1247.

Research output: Contribution to journalArticle

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Kaushal G, Jeong H, Maheshwaram S, Manhas SK, Dasgupta S, Jung S. Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectronics Journal. 2015 Dec 1;46(12):1239-1247. https://doi.org/10.1016/j.mejo.2015.10.016