Proposed herein is a new technique of activation for the backplane of low-temperature amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) by applying a bias voltage to gate, source, and drain electrodes and simultaneously annealing them at 150°C. This ‘voltage bias activation’ can be an effective method of reducing the backplane processing temperature from 300°C to 150°C. Compared with the reference a-IGZO TFTs fabricated at 300°C, the a-IGZO TFTs fabricated through voltage bias activation showed sufficient switching characteristics: 10.39 cm2/Vs field effect mobility, 0.41 V/decade subthreshold swing, and 3.65 × 107 on/off ratio. These results were analyzed thermodynamically using infrared micro-thermography. In the case of the positive gate voltage bias condition, the maximum temperature of the a-IGZO channel increased to 48°C, and this additional annealing effect and activation energy lowering compensated for the insufficient thermal energy of annealing at a low temperature (150°C). With this approach, a-IGZO TFTs were successfully fabricated at a low temperature.
All Science Journal Classification (ASJC) codes
- Materials Science(all)
- Electrical and Electronic Engineering