Low-temperature solution processing of AlInZnO/InZnO dual-channel thin-film transistors

Kyung Min Kim; Woong Hee Jeong; Dong Lim Kim; You Seung Rim; Yuri Choi; Myung Kwan Ryu; Kyung Bae Park; Hyun Jae Kim

doi:10.1109/LED.2011.2160612

Low-temperature solution processing of AlInZnO/InZnO dual-channel thin-film transistors

Kyung Min Kim, Woong Hee Jeong, Dong Lim Kim, You Seung Rim, Yuri Choi, Myung Kwan Ryu, Kyung Bae Park, Hyun Jae Kim

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article

51 Citations (Scopus)

Abstract

In this letter, we proposed solution-processed AlInZnO (AIZO)/InZnO (IZO) dual-channel thin-film transistors to realize both proper switching behavior and competitive device performance at the low annealing temperature of 350°C. A thin IZO layer provides a higher carrier concentration, thereby maximizing the charge accumulation and yielding high saturation mobility μ_sat, whereas a thick AIZO layer controls the charge conductance resulting in suitable threshold voltage V_th. We therefore obtain excellent device characteristics at 350 °C with μ_sat of 1.57 cm ²V_s, V_th of 1.28 V, an on/off ratio of ∼1.4 ×10⁷, and a subthreshold gate swing of 0.59 V/dec.

Original language	English
Article number	5957259
Pages (from-to)	1242-1244
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	32
Issue number	9
DOIs	https://doi.org/10.1109/LED.2011.2160612
Publication status	Published - 2011 Sep 1

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/LED.2011.2160612

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Kim, K. M., Jeong, W. H., Kim, D. L., Rim, Y. S., Choi, Y., Ryu, M. K., Park, K. B., & Kim, H. J. (2011). Low-temperature solution processing of AlInZnO/InZnO dual-channel thin-film transistors. IEEE Electron Device Letters, 32(9), 1242-1244. [5957259]. https://doi.org/10.1109/LED.2011.2160612

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abstract = "In this letter, we proposed solution-processed AlInZnO (AIZO)/InZnO (IZO) dual-channel thin-film transistors to realize both proper switching behavior and competitive device performance at the low annealing temperature of 350°C. A thin IZO layer provides a higher carrier concentration, thereby maximizing the charge accumulation and yielding high saturation mobility μsat, whereas a thick AIZO layer controls the charge conductance resulting in suitable threshold voltage Vth. We therefore obtain excellent device characteristics at 350 °C with μsat of 1.57 cm 2Vs, Vth of 1.28 V, an on/off ratio of ∼1.4 ×107, and a subthreshold gate swing of 0.59 V/dec.",

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AU - Ryu, Myung Kwan

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AU - Kim, Hyun Jae

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