Low-voltage-driven top-gate ZnO thin-film transistors with polymer/high-k oxide double-layer dielectric

Kimoon Lee, Jae Hoon Kim, Seongil Im, Chang Su Kim, Hong Koo Baik

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Abstract

The authors report on the fabrication of a low-voltage-driven top-gate ZnO thin-film transistor with a polymer/high-k oxide double-layer dielectric. Hybrid double-layer dielectric (k= ∼ 9.8) was formed on patterned ZnO through sequential deposition processes: spin casting of 45-nm-thin poly-4-vinylphenol and e-beam evaporation of 50-nm-thick amorphous high-k oxide (CeO 2-SiO2 mixture Room-temperature-deposited ZnO channel exhibits much rougher surfaces compared to that of 100°C deposited ZnO, so that enhanced device performances were achieved from a ZnO thin-film transistor (TFT) prepared with 100°C deposited ZnO: ∼0.48 cm2/V s for field-effect mobility and ∼5 × 103 for on/off current ratio. Adopting our top-gate ZnO-TFT, a load-resistance inverter was set up and demonstrated decent static and dynamic operations at 3 V.

Original languageEnglish
Article number133507
JournalApplied Physics Letters
Volume89
Issue number13
DOIs
Publication statusPublished - 2006

Bibliographical note

Funding Information:
The authors acknowledge the financial support from KOSEF (Program Nos. M1-0214-00-0228 and R01-2006-000-11277-0), KITECH, and the support from Brain Korea 21 Program. One of the authors (J.H.K.) acknowledges the support from eSSC at Postech funded by KOSEF/MOST.

All Science Journal Classification (ASJC) codes

  • Physics and Astronomy (miscellaneous)

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