Low-voltage green transistor using ultra shallow junction and hetero-tunneling

Anupama Bowonder, Pratik Patel, Kanghoon Jeon, Jungwoo Oh, Prashant Majhi, Hsing Huang Tseng, Chenming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

Original languageEnglish
Title of host publicationIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology
Pages93-96
Number of pages4
DOIs
Publication statusPublished - 2008 Sep 8
EventIWJT-2008 - International Workshop on Junction Technology - Shanghai, China
Duration: 2008 May 152008 May 16

Other

OtherIWJT-2008 - International Workshop on Junction Technology
CountryChina
CityShanghai
Period08/5/1508/5/16

Fingerprint

Tunnels
Transistors
Low power electronics
Electric potential
Heterojunctions
Metals

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Bowonder, A., Patel, P., Jeon, K., Oh, J., Majhi, P., Tseng, H. H., & Hu, C. (2008). Low-voltage green transistor using ultra shallow junction and hetero-tunneling. In IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology (pp. 93-96). [4540025] https://doi.org/10.1109/IWJT.2008.4540025
Bowonder, Anupama ; Patel, Pratik ; Jeon, Kanghoon ; Oh, Jungwoo ; Majhi, Prashant ; Tseng, Hsing Huang ; Hu, Chenming. / Low-voltage green transistor using ultra shallow junction and hetero-tunneling. IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology. 2008. pp. 93-96
@inproceedings{95266f4ec18b43adb830c571f8b6d947,
title = "Low-voltage green transistor using ultra shallow junction and hetero-tunneling",
abstract = "A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.",
author = "Anupama Bowonder and Pratik Patel and Kanghoon Jeon and Jungwoo Oh and Prashant Majhi and Tseng, {Hsing Huang} and Chenming Hu",
year = "2008",
month = "9",
day = "8",
doi = "10.1109/IWJT.2008.4540025",
language = "English",
isbn = "9781424417384",
pages = "93--96",
booktitle = "IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology",

}

Bowonder, A, Patel, P, Jeon, K, Oh, J, Majhi, P, Tseng, HH & Hu, C 2008, Low-voltage green transistor using ultra shallow junction and hetero-tunneling. in IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology., 4540025, pp. 93-96, IWJT-2008 - International Workshop on Junction Technology, Shanghai, China, 08/5/15. https://doi.org/10.1109/IWJT.2008.4540025

Low-voltage green transistor using ultra shallow junction and hetero-tunneling. / Bowonder, Anupama; Patel, Pratik; Jeon, Kanghoon; Oh, Jungwoo; Majhi, Prashant; Tseng, Hsing Huang; Hu, Chenming.

IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology. 2008. p. 93-96 4540025.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Low-voltage green transistor using ultra shallow junction and hetero-tunneling

AU - Bowonder, Anupama

AU - Patel, Pratik

AU - Jeon, Kanghoon

AU - Oh, Jungwoo

AU - Majhi, Prashant

AU - Tseng, Hsing Huang

AU - Hu, Chenming

PY - 2008/9/8

Y1 - 2008/9/8

N2 - A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

AB - A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

UR - http://www.scopus.com/inward/record.url?scp=50849096106&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50849096106&partnerID=8YFLogxK

U2 - 10.1109/IWJT.2008.4540025

DO - 10.1109/IWJT.2008.4540025

M3 - Conference contribution

SN - 9781424417384

SP - 93

EP - 96

BT - IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology

ER -

Bowonder A, Patel P, Jeon K, Oh J, Majhi P, Tseng HH et al. Low-voltage green transistor using ultra shallow junction and hetero-tunneling. In IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology. 2008. p. 93-96. 4540025 https://doi.org/10.1109/IWJT.2008.4540025