Low-voltage green transistor using ultra shallow junction and hetero-tunneling

Anupama Bowonder, Pratik Patel, Kanghoon Jeon, Jungwoo Oh, Prashant Majhi, Hsing Huang Tseng, Chenming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

35 Citations (Scopus)

Abstract

A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

Original languageEnglish
Title of host publicationIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology
Pages93-96
Number of pages4
DOIs
Publication statusPublished - 2008 Sep 8
EventIWJT-2008 - International Workshop on Junction Technology - Shanghai, China
Duration: 2008 May 152008 May 16

Publication series

NameIWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology

Other

OtherIWJT-2008 - International Workshop on Junction Technology
CountryChina
CityShanghai
Period08/5/1508/5/16

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Bowonder, A., Patel, P., Jeon, K., Oh, J., Majhi, P., Tseng, H. H., & Hu, C. (2008). Low-voltage green transistor using ultra shallow junction and hetero-tunneling. In IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology (pp. 93-96). [4540025] (IWJT-2008 - Extended Abstracts 2008 International Workshop on Junction Technology). https://doi.org/10.1109/IWJT.2008.4540025