Low-voltage, high-speed circuit designs for gigabit DRAM's

Kyuchan Lee, Changhyun Kim, Dong Ryul Ryu, Jai Hoon Sim, Sang Bo Lee, Byung Sik Moon, Keum Yong Kim, Nam Jong Kim, Seung Moon Yoo, Hongil Yoon, Jei Hwan Yoo, Soo In Cho

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

This paper describes several new circuit design techniques for low V CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV BL) as well as the V GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t RAC) of 28 ns at V CC = 1.5 V and T = 25°C has been obtained.

Original languageEnglish
Pages (from-to)642-647
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume32
Issue number5
DOIs
Publication statusPublished - 1997 May 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Lee, K., Kim, C., Ryu, D. R., Sim, J. H., Lee, S. B., Moon, B. S., Kim, K. Y., Kim, N. J., Yoo, S. M., Yoon, H., Yoo, J. H., & Cho, S. I. (1997). Low-voltage, high-speed circuit designs for gigabit DRAM's. IEEE Journal of Solid-State Circuits, 32(5), 642-647. https://doi.org/10.1109/4.568824