There is a fundamental tradeoff between processor performance and lifetime reliability. High throughput operations increase power and heat dissipations that have adverse impacts on lifetime reliability. On the contrary, lifetime reliability favors low utilization to reduce stresses and avoid failures. A key challenge of understanding this tradeoff is in connecting application characteristics to device-level degradation behaviors. Using a full-system microarchitecture and physics simulation, the performance-reliability tradeoff in a multicore processor is analyzed by introducing a metric, throughput-lifetime product (TLP). A finding reveals that reducing the variance of degradation distribution on the multicore die leads to effectively enhancing processor lifetime with minimal impact on performance. This concept is referred to as dynamic reliability variance management (DRVM). We discuss three possible microarchitectural techniques that perform DRVM and improve the TLP; i) phase-aware thread migration, ii) dynamic voltage scaling, and iii) turbo-mode execution combined with DRVM. The simulation results with selected PARSEC and SPLASH-2 benchmarks show that DRVM techniques improve processor lifetime up to 15% or enhance the throughput-lifetime tradeoff by 12% without adding extra design margins or spare components on the multicore die.
|Title of host publication||2015 IEEE International Reliability Physics Symposium, IRPS 2015|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2015 May 26|
|Event||IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States|
Duration: 2015 Apr 19 → 2015 Apr 23
|Name||IEEE International Reliability Physics Symposium Proceedings|
|Other||IEEE International Reliability Physics Symposium, IRPS 2015|
|Period||15/4/19 → 15/4/23|
Bibliographical notePublisher Copyright:
© 2015 IEEE.
All Science Journal Classification (ASJC) codes