Managing performance-reliability tradeoffs in multicore processors

William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

There is a fundamental tradeoff between processor performance and lifetime reliability. High throughput operations increase power and heat dissipations that have adverse impacts on lifetime reliability. On the contrary, lifetime reliability favors low utilization to reduce stresses and avoid failures. A key challenge of understanding this tradeoff is in connecting application characteristics to device-level degradation behaviors. Using a full-system microarchitecture and physics simulation, the performance-reliability tradeoff in a multicore processor is analyzed by introducing a metric, throughput-lifetime product (TLP). A finding reveals that reducing the variance of degradation distribution on the multicore die leads to effectively enhancing processor lifetime with minimal impact on performance. This concept is referred to as dynamic reliability variance management (DRVM). We discuss three possible microarchitectural techniques that perform DRVM and improve the TLP; i) phase-aware thread migration, ii) dynamic voltage scaling, and iii) turbo-mode execution combined with DRVM. The simulation results with selected PARSEC and SPLASH-2 benchmarks show that DRVM techniques improve processor lifetime up to 15% or enhance the throughput-lifetime tradeoff by 12% without adding extra design margins or spare components on the multicore die.

Original languageEnglish
Title of host publication2015 IEEE International Reliability Physics Symposium, IRPS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3C11-3C17
ISBN (Electronic)9781467373623
DOIs
Publication statusPublished - 2015 May 26
EventIEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States
Duration: 2015 Apr 192015 Apr 23

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2015-May
ISSN (Print)1541-7026

Other

OtherIEEE International Reliability Physics Symposium, IRPS 2015
CountryUnited States
CityMonterey
Period15/4/1915/4/23

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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    Song, W. J., Mukhopadhyay, S., & Yalamanchili, S. (2015). Managing performance-reliability tradeoffs in multicore processors. In 2015 IEEE International Reliability Physics Symposium, IRPS 2015 (pp. 3C11-3C17). [7112707] (IEEE International Reliability Physics Symposium Proceedings; Vol. 2015-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2015.7112707