Marker layout for optimizing the overlay alignment in a photolithography process

Ki Bum Lee, Chang Ouk Kim

Research output: Contribution to journalArticle

Abstract

In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer yield. To enhance the alignment precision, an overlay metrology system measures the overlay error at some markers on the wafer, and the error information is used for constructing an overlay correction model. During the overlay alignment, the layout of the markers has a significant impact on the correction of the overlay error. After the maximum number of available markers has been determined based on the quality and turn-around time of the target device, the positions of those markers should be determined in such a way that the overlay error correction model shows robust performance for future wafers. In this paper, we propose a sparse particle swarm optimization algorithm to find an optimal marker layout in terms of robust performance characterized by the overlay error prediction and irregularity of marker positions. In the experiment, the performance of the marker layouts suggested by several search algorithms was tested on three different layers, and the proposed algorithm demonstrated superiority over the other algorithms.

Original languageEnglish
Article number8675528
Pages (from-to)212-219
Number of pages8
JournalIEEE Transactions on Semiconductor Manufacturing
Volume32
Issue number2
DOIs
Publication statusPublished - 2019 May 1

Fingerprint

Photolithography
photolithography
layouts
markers
alignment
wafers
Turnaround time
Error correction
Particle swarm optimization (PSO)
Masks
Fabrication
irregularities
metrology
masks
Experiments
fabrication
optimization
predictions

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

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Marker layout for optimizing the overlay alignment in a photolithography process. / Lee, Ki Bum; Kim, Chang Ouk.

In: IEEE Transactions on Semiconductor Manufacturing, Vol. 32, No. 2, 8675528, 01.05.2019, p. 212-219.

Research output: Contribution to journalArticle

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