Matrix multiplications on the memory-based processor array

Mi Jung Noh, Youngsik Kim, Tack Don Han, Shin Dug Kim, Sung Bong Yang

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

A memory-based processor array (MPA) for matrix multiplications is designed as an effective array architecture. Also a mapping algorithm to implement matrix multiplication on the MPA system is proposed. One outstanding feature of the MPA system is that it can be easily integrated into any host system via memory interface. Specifically, the MPA system provides an efficient mechanism for its local memory accesses allowed by the row basis and the column basis using the hybrid row and column decoding, which is suitable for matrix multiplications. An important factor to improve performance in the processor array is to reduce the communication time among processing units and this can be achieved through efficient memory structure. The proposed architecture and its corresponding algorithm are turned out to be better than others by performance evaluation. And the MPA system also provides a new platform for computing a variety of linear algebra applications.

Original languageEnglish
Pages377-382
Number of pages6
Publication statusPublished - 1997 Jan 1
EventProceedings of the 1997 2nd High Performance Computing on the Information Superhighway, HPC Asia'97 - Seoul, South Korea
Duration: 1997 Apr 281997 May 2

Other

OtherProceedings of the 1997 2nd High Performance Computing on the Information Superhighway, HPC Asia'97
CitySeoul, South Korea
Period97/4/2897/5/2

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All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Noh, M. J., Kim, Y., Han, T. D., Kim, S. D., & Yang, S. B. (1997). Matrix multiplications on the memory-based processor array. 377-382. Paper presented at Proceedings of the 1997 2nd High Performance Computing on the Information Superhighway, HPC Asia'97, Seoul, South Korea, .