Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.
|Number of pages||6|
|Journal||Journal of Electronic Testing: Theory and Applications (JETTA)|
|Publication status||Published - 2007 Aug|
Bibliographical noteFunding Information:
This work was supported by the Korea Science and Engineering Foundation Grant funded by the Korea government (MOST) No. R01-2006-000-11038-0.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering