MDSI: Signal integrity interconnect fault modeling and testing for SoCs

Sunghoon Chun, Yongjoon Kim, Sungho Kang

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

Original languageEnglish
Pages (from-to)357-362
Number of pages6
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume23
Issue number4
DOIs
Publication statusPublished - 2007 Aug 1

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Testing
Topology

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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MDSI : Signal integrity interconnect fault modeling and testing for SoCs. / Chun, Sunghoon; Kim, Yongjoon; Kang, Sungho.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 23, No. 4, 01.08.2007, p. 357-362.

Research output: Contribution to journalArticle

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