Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency

William J. Song, Alper Buyuktosunoglu, Chen Yong Cher, Pradip Bose

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

It is generally perceived that heterogeneous multicore processors will provide better performance and power efficiency over conventional homogeneous cores. However, heterogeneity can also be achieved within a homogeneous core design, instantiated under different voltage-frequency settings or per-core simultaneous multi-treading (SMT) modes. In this paper, we pursue an architectural study motivated by the question, "Can we get by with a single, complex SMT-equipped core design that can operate at different voltage-frequency points? Or, is it mandatory to invest into two different core types, one complex and the other simple?" We propose a systematic, measurement-driven methodology to evaluate processor heterogeneity options. Our analysis particularly focuses on the domain of real-time constrained embedded processors. The study is based on a direct measurement of two real processors; one that uses simple in-order cores, and another that uses complex out-of-order cores. The effect of heterogeneous core composition (consisting of complex and simple cores in the same chip) is analytically projected from measurements gleaned from the two different systems. Our analysis yields new interesting insights. When dealing with two core types without SMT enabled, true core heterogeneity does not necessarily provide better performance or power efficiency under area and power constraints. If the complex-core homogeneous processor invokes SMT, it outperforms true heterogeneity by offering 28% better power efficiency, assuming that simple cores in the heterogeneous system operate only in single-threaded mode without SMT capability. If the small cores employ SMT, true heterogeneity yields 32% better power efficiency than the homogeneous processor with SMT.

Original languageEnglish
Title of host publicationISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages284-289
Number of pages6
ISBN (Electronic)9781450341851
DOIs
Publication statusPublished - 2016 Aug 8
Event21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016 - San Francisco, United States
Duration: 2016 Aug 82016 Aug 10

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

Other21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016
CountryUnited States
CitySan Francisco
Period16/8/816/8/10

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Fingerprint Dive into the research topics of 'Measurement-Driven Methodology for Evaluating Processor Heterogeneity Options for Power-Performance Efficiency'. Together they form a unique fingerprint.

Cite this