Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network

Sangheon Kwon; Kyungmin Lee; Yoonsoo Kim; Kyungah Kim; Changmin Lee; Won Woo Ro

doi:10.1109/ICCE-Asia.2016.7804818

Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network

Sangheon Kwon, Kyungmin Lee, Yoonsoo Kim, Kyungah Kim, Changmin Lee, Won Woo Ro

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

Hardware accelerators for convolutional neural network (CNN) accompany a large amount of SRAM in order to reduce the number of expensive off-chip DRAM accesses. This design trend gives implications to architects: The SRAM area will dominate the entire chip area for the future CNN accelerators. Since the probability of soft errors such as energetic particle strikes goes as the density of SRAM, errors on memory sub-system will become a major concern as process technology scales. In this paper, we investigate the necessity of a faulttolerant memory system, against such soft errors, in hardware accelerated neural network. We found that convolutional layers have different error tolerance from each other. The error tolerance of a layer tends to get worse as it goes on the output layer.

Original language	English
Title of host publication	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509027439
DOIs	https://doi.org/10.1109/ICCE-Asia.2016.7804818
Publication status	Published - 2017 Jan 3
Event	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 - Seoul, Korea, Republic of Duration: 2016 Oct 26 → 2016 Oct 28

Publication series

Name	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016

Other

Other	2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016
Country/Territory	Korea, Republic of
City	Seoul
Period	16/10/26 → 16/10/28

Bibliographical note

Funding Information:
This work was supported by IDEC and ICT R&D program of MSIP/IITP [B0101-16-0233, Smart Networking Core Technology Development]. W. W. Ro is the corresponding author.

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ICCE-Asia.2016.7804818

Cite this

Kwon, S., Lee, K., Kim, Y., Kim, K., Lee, C., & Ro, W. W. (2017). Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network. In 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 [7804818] (2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCE-Asia.2016.7804818

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abstract = "Hardware accelerators for convolutional neural network (CNN) accompany a large amount of SRAM in order to reduce the number of expensive off-chip DRAM accesses. This design trend gives implications to architects: The SRAM area will dominate the entire chip area for the future CNN accelerators. Since the probability of soft errors such as energetic particle strikes goes as the density of SRAM, errors on memory sub-system will become a major concern as process technology scales. In this paper, we investigate the necessity of a faulttolerant memory system, against such soft errors, in hardware accelerated neural network. We found that convolutional layers have different error tolerance from each other. The error tolerance of a layer tends to get worse as it goes on the output layer.",

author = "Sangheon Kwon and Kyungmin Lee and Yoonsoo Kim and Kyungah Kim and Changmin Lee and Ro, {Won Woo}",

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Kwon, S, Lee, K, Kim, Y, Kim, K, Lee, C & Ro, WW 2017, Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network. in 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016., 7804818, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016, Seoul, Korea, Republic of, 16/10/26. https://doi.org/10.1109/ICCE-Asia.2016.7804818

Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network. / Kwon, Sangheon; Lee, Kyungmin; Kim, Yoonsoo et al.

2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7804818 (2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Kwon S, Lee K, Kim Y, Kim K, Lee C, Ro WW. Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network. In 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016. Institute of Electrical and Electronics Engineers Inc. 2017. 7804818. (2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016). doi: 10.1109/ICCE-Asia.2016.7804818

Measuring error-Tolerance in SRAM architecture on hardware accelerated neural network

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