Hardware accelerators for convolutional neural network (CNN) accompany a large amount of SRAM in order to reduce the number of expensive off-chip DRAM accesses. This design trend gives implications to architects: The SRAM area will dominate the entire chip area for the future CNN accelerators. Since the probability of soft errors such as energetic particle strikes goes as the density of SRAM, errors on memory sub-system will become a major concern as process technology scales. In this paper, we investigate the necessity of a faulttolerant memory system, against such soft errors, in hardware accelerated neural network. We found that convolutional layers have different error tolerance from each other. The error tolerance of a layer tends to get worse as it goes on the output layer.
|Title of host publication||2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Publication status||Published - 2017 Jan 3|
|Event||2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 - Seoul, Korea, Republic of|
Duration: 2016 Oct 26 → 2016 Oct 28
|Name||2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016|
|Other||2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016|
|Country/Territory||Korea, Republic of|
|Period||16/10/26 → 16/10/28|
Bibliographical noteFunding Information:
This work was supported by IDEC and ICT R&D program of MSIP/IITP [B0101-16-0233, Smart Networking Core Technology Development]. W. W. Ro is the corresponding author.
© 2016 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering