Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

Jeff Huang, Paul D. Kirsch, Jungwoo Oh, Se Hoon Lee, Prashant Majhi, H. Rusty Harris, Daivd C. Gilmer, Gennadi Bersuker, Dawei Heh, Chang Seo Park, Chanro Park, Hsing Huang Tseng, Raj Jammy

Research output: Contribution to journalArticle

15 Citations (Scopus)

Abstract

This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

Original languageEnglish
Pages (from-to)285-287
Number of pages3
JournalIEEE Electron Device Letters
Volume30
Issue number3
DOIs
Publication statusPublished - 2009 Feb 12

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Leakage currents
Oxides
Metals
Nitridation
Fabrication
Diffusion barriers
Transistors
Plasmas
Oxidation
Substrates

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Huang, Jeff ; Kirsch, Paul D. ; Oh, Jungwoo ; Lee, Se Hoon ; Majhi, Prashant ; Harris, H. Rusty ; Gilmer, Daivd C. ; Bersuker, Gennadi ; Heh, Dawei ; Park, Chang Seo ; Park, Chanro ; Tseng, Hsing Huang ; Jammy, Raj. / Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe. In: IEEE Electron Device Letters. 2009 ; Vol. 30, No. 3. pp. 285-287.
@article{b33efdad534b408793fd8d47a60eb0ee,
title = "Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe",
abstract = "This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3{\%}) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.",
author = "Jeff Huang and Kirsch, {Paul D.} and Jungwoo Oh and Lee, {Se Hoon} and Prashant Majhi and Harris, {H. Rusty} and Gilmer, {Daivd C.} and Gennadi Bersuker and Dawei Heh and Park, {Chang Seo} and Chanro Park and Tseng, {Hsing Huang} and Raj Jammy",
year = "2009",
month = "2",
day = "12",
doi = "10.1109/LED.2008.2011754",
language = "English",
volume = "30",
pages = "285--287",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

Huang, J, Kirsch, PD, Oh, J, Lee, SH, Majhi, P, Harris, HR, Gilmer, DC, Bersuker, G, Heh, D, Park, CS, Park, C, Tseng, HH & Jammy, R 2009, 'Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe', IEEE Electron Device Letters, vol. 30, no. 3, pp. 285-287. https://doi.org/10.1109/LED.2008.2011754

Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe. / Huang, Jeff; Kirsch, Paul D.; Oh, Jungwoo; Lee, Se Hoon; Majhi, Prashant; Harris, H. Rusty; Gilmer, Daivd C.; Bersuker, Gennadi; Heh, Dawei; Park, Chang Seo; Park, Chanro; Tseng, Hsing Huang; Jammy, Raj.

In: IEEE Electron Device Letters, Vol. 30, No. 3, 12.02.2009, p. 285-287.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

AU - Huang, Jeff

AU - Kirsch, Paul D.

AU - Oh, Jungwoo

AU - Lee, Se Hoon

AU - Majhi, Prashant

AU - Harris, H. Rusty

AU - Gilmer, Daivd C.

AU - Bersuker, Gennadi

AU - Heh, Dawei

AU - Park, Chang Seo

AU - Park, Chanro

AU - Tseng, Hsing Huang

AU - Jammy, Raj

PY - 2009/2/12

Y1 - 2009/2/12

N2 - This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

AB - This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

UR - http://www.scopus.com/inward/record.url?scp=62549137369&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62549137369&partnerID=8YFLogxK

U2 - 10.1109/LED.2008.2011754

DO - 10.1109/LED.2008.2011754

M3 - Article

AN - SCOPUS:62549137369

VL - 30

SP - 285

EP - 287

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 3

ER -