Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

Jeff Huang, Paul D. Kirsch, Jungwoo Oh, Se Hoon Lee, Prashant Majhi, H. Rusty Harris, Daivd C. Gilmer, Gennadi Bersuker, Dawei Heh, Chang Seo Park, Chanro Park, Hsing Huang Tseng, Raj Jammy

Research output: Contribution to journalArticle

15 Citations (Scopus)

Abstract

This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

Original languageEnglish
Pages (from-to)285-287
Number of pages3
JournalIEEE Electron Device Letters
Volume30
Issue number3
DOIs
Publication statusPublished - 2009 Feb 12

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Huang, J., Kirsch, P. D., Oh, J., Lee, S. H., Majhi, P., Harris, H. R., Gilmer, D. C., Bersuker, G., Heh, D., Park, C. S., Park, C., Tseng, H. H., & Jammy, R. (2009). Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe. IEEE Electron Device Letters, 30(3), 285-287. https://doi.org/10.1109/LED.2008.2011754