Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

J. Huang, P. D. Kirsch, J. Oh, S. H. Lee, J. Price, P. Majhi, H. R. Harris, D. C. Gilmer, D. Q. Kelly, P. Sivasubramani, G. Bersuker, D. Heh, C. Young, C. S. Park, Y. N. Tan, N. Goel, C. Park, P. Y. Hung, P. Lysaght, K. J. ChoiB. J. Cho, H. H. Tseng, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

15 Citations (Scopus)

Abstract

For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (≥4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.

Original languageEnglish
Title of host publication2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages82-83
Number of pages2
DOIs
Publication statusPublished - 2008 Sep 23
Event2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States
Duration: 2008 Jun 17 → 2008 Jun 19

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
CountryUnited States
CityHonolulu, HI
Period08/6/17 → 08/6/19

Fingerprint

Leakage currents
Nitridation
Gate dielectrics
Metals
Doping (additives)
Oxidation
Ions
Processing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Huang, J., Kirsch, P. D., Oh, J., Lee, S. H., Price, J., Majhi, P., ... Jammy, R. (2008). Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT. In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT (pp. 82-83). [4588571] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588571
Huang, J. ; Kirsch, P. D. ; Oh, J. ; Lee, S. H. ; Price, J. ; Majhi, P. ; Harris, H. R. ; Gilmer, D. C. ; Kelly, D. Q. ; Sivasubramani, P. ; Bersuker, G. ; Heh, D. ; Young, C. ; Park, C. S. ; Tan, Y. N. ; Goel, N. ; Park, C. ; Hung, P. Y. ; Lysaght, P. ; Choi, K. J. ; Cho, B. J. ; Tseng, H. H. ; Lee, B. H. ; Jammy, R. / Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT. 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. pp. 82-83 (Digest of Technical Papers - Symposium on VLSI Technology).
@inproceedings{426fb9114513458e9693379ccb0b8552,
title = "Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT",
abstract = "For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (≥4{\%}) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.",
author = "J. Huang and Kirsch, {P. D.} and J. Oh and Lee, {S. H.} and J. Price and P. Majhi and Harris, {H. R.} and Gilmer, {D. C.} and Kelly, {D. Q.} and P. Sivasubramani and G. Bersuker and D. Heh and C. Young and Park, {C. S.} and Tan, {Y. N.} and N. Goel and C. Park and Hung, {P. Y.} and P. Lysaght and Choi, {K. J.} and Cho, {B. J.} and Tseng, {H. H.} and Lee, {B. H.} and R. Jammy",
year = "2008",
month = "9",
day = "23",
doi = "10.1109/VLSIT.2008.4588571",
language = "English",
isbn = "9781424418053",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
pages = "82--83",
booktitle = "2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT",

}

Huang, J, Kirsch, PD, Oh, J, Lee, SH, Price, J, Majhi, P, Harris, HR, Gilmer, DC, Kelly, DQ, Sivasubramani, P, Bersuker, G, Heh, D, Young, C, Park, CS, Tan, YN, Goel, N, Park, C, Hung, PY, Lysaght, P, Choi, KJ, Cho, BJ, Tseng, HH, Lee, BH & Jammy, R 2008, Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT. in 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT., 4588571, Digest of Technical Papers - Symposium on VLSI Technology, pp. 82-83, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, Honolulu, HI, United States, 08/6/17. https://doi.org/10.1109/VLSIT.2008.4588571

Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT. / Huang, J.; Kirsch, P. D.; Oh, J.; Lee, S. H.; Price, J.; Majhi, P.; Harris, H. R.; Gilmer, D. C.; Kelly, D. Q.; Sivasubramani, P.; Bersuker, G.; Heh, D.; Young, C.; Park, C. S.; Tan, Y. N.; Goel, N.; Park, C.; Hung, P. Y.; Lysaght, P.; Choi, K. J.; Cho, B. J.; Tseng, H. H.; Lee, B. H.; Jammy, R.

2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 82-83 4588571 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

AU - Huang, J.

AU - Kirsch, P. D.

AU - Oh, J.

AU - Lee, S. H.

AU - Price, J.

AU - Majhi, P.

AU - Harris, H. R.

AU - Gilmer, D. C.

AU - Kelly, D. Q.

AU - Sivasubramani, P.

AU - Bersuker, G.

AU - Heh, D.

AU - Young, C.

AU - Park, C. S.

AU - Tan, Y. N.

AU - Goel, N.

AU - Park, C.

AU - Hung, P. Y.

AU - Lysaght, P.

AU - Choi, K. J.

AU - Cho, B. J.

AU - Tseng, H. H.

AU - Lee, B. H.

AU - Jammy, R.

PY - 2008/9/23

Y1 - 2008/9/23

N2 - For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (≥4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.

AB - For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (≥4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.

UR - http://www.scopus.com/inward/record.url?scp=51949092784&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51949092784&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2008.4588571

DO - 10.1109/VLSIT.2008.4588571

M3 - Conference contribution

AN - SCOPUS:51949092784

SN - 9781424418053

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 82

EP - 83

BT - 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT

ER -

Huang J, Kirsch PD, Oh J, Lee SH, Price J, Majhi P et al. Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT. In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT. 2008. p. 82-83. 4588571. (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588571

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