Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

J. Huang, P. D. Kirsch, J. Oh, S. H. Lee, J. Price, P. Majhi, H. R. Harris, D. C. Gilmer, D. Q. Kelly, P. Sivasubramani, G. Bersuker, D. Heh, C. Young, C. S. Park, Y. N. Tan, N. Goel, C. Park, P. Y. Hung, P. Lysaght, K. J. ChoiB. J. Cho, H. H. Tseng, B. H. Lee, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (≥4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.

Original languageEnglish
Title of host publication2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
Pages82-83
Number of pages2
DOIs
Publication statusPublished - 2008
Event2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States
Duration: 2008 Jun 172008 Jun 19

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
CountryUnited States
CityHonolulu, HI
Period08/6/1708/6/19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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    Huang, J., Kirsch, P. D., Oh, J., Lee, S. H., Price, J., Majhi, P., Harris, H. R., Gilmer, D. C., Kelly, D. Q., Sivasubramani, P., Bersuker, G., Heh, D., Young, C., Park, C. S., Tan, Y. N., Goel, N., Park, C., Hung, P. Y., Lysaght, P., ... Jammy, R. (2008). Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT. In 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT (pp. 82-83). [4588571] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2008.4588571