Memory based processor array for artificial neural networks

Youngsik Kim, Mi Jung Noh, Tack Don Han, Shin Dug Kim, Sung Bong Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper an effective memory-processor integrated architecture, called memory based processor array for artificial neural networks (MPAA), is proposed. The MPAA can be easily integrated into any host system via memory interface. Specifically, the MPAA system provides an efficient mechanism for its local memory accesses allowed by the row basis and the column basis using the hybrid row and column decoding, which is suitable for the computation model of ANNs such as the accessing and alignment patterns given for matrix-by-vector operations. Mapping algorithms to implement the multilayer perceptron with backpropagation learning on the MPAA system are also provided. The proposed algorithms support both neuron and layer level parallelisms which allow the MPAA system to operate the learning phase as well as the recall phase in the pipelined fashion. Performance evaluation is provided by detailed comparison in terms of two metrics such as the cost and the number of computation steps.

Original languageEnglish
Title of host publication1997 IEEE International Conference on Neural Networks, ICNN 1997
Pages969-974
Number of pages6
DOIs
Publication statusPublished - 1997 Dec 1
Event1997 IEEE International Conference on Neural Networks, ICNN 1997 - Houston, TX, United States
Duration: 1997 Jun 91997 Jun 12

Publication series

NameIEEE International Conference on Neural Networks - Conference Proceedings
Volume2
ISSN (Print)1098-7576

Other

Other1997 IEEE International Conference on Neural Networks, ICNN 1997
CountryUnited States
CityHouston, TX
Period97/6/997/6/12

All Science Journal Classification (ASJC) codes

  • Software

Fingerprint Dive into the research topics of 'Memory based processor array for artificial neural networks'. Together they form a unique fingerprint.

  • Cite this

    Kim, Y., Noh, M. J., Han, T. D., Kim, S. D., & Yang, S. B. (1997). Memory based processor array for artificial neural networks. In 1997 IEEE International Conference on Neural Networks, ICNN 1997 (pp. 969-974). [616157] (IEEE International Conference on Neural Networks - Conference Proceedings; Vol. 2). https://doi.org/10.1109/ICNN.1997.616157