Memory ECC architecutre utilizing memory column spares

Jong Hyuk Park, Joon Sung Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Advanced process technology allows high memory density. However, the memory cell shrinkage introduces more memory defects and this causes a memory yield problem. To overcome the issue, memory ECC has become a critical solution. This paper proposes a hardware architecture to support memory ECC utilizing memory spares. Overheads imposed by the proposed architecture are analyzed and compared against conventional non-ECC memory architecture.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages359-360
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Dec 27
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 232016 Oct 26

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Other

Other13th International SoC Design Conference, ISOCC 2016
CountryKorea, Republic of
CityJeju
Period16/10/2316/10/26

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Instrumentation

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  • Cite this

    Park, J. H., & Yang, J. S. (2016). Memory ECC architecutre utilizing memory column spares. In ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things (pp. 359-360). [7799826] (ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2016.7799826