A memory-efficient and high-speed low-density parity-check (LDPC) encoder is proposed, which uses a memory efficient parity-check matrix, called a differential parity-check matrix. The partially parallel architecture is also proposed for use in high-speed encoding. The proposed two-stage cyclic shifter is appropriate for a differential parity-check matrix and partially parallel architecture with low complexity. The proposed LDPC encoder is implemented with a 21 reduction in memory. The speed of the proposed partially parallel LDPC encoder is three times faster than the existing serial LDPC encoder.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering