Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors

Gi Ho Park, Oh Young Kwon, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang

Research output: Contribution to journalArticle

Abstract

The performance of conventional instruction prefetching mechanisms (IPMs) is analyzed in this paper based on two performance factors, i.e., the cache miss ratio and the average access time for successfully prefetched blocks. Although significant performance improvement (PI) can be obtained by improving these two factors, most conventional prefetching mechanisms improve only one factor out of these two factors. Fetching multiple blocks for a prefetch request and prefetching the sequentially next block together with the block that causes a cache miss in lookahead prefetching (LP) are proposed to improve both these factors. A new method to initiate a prefetch request earlier with no degradation of the prefetch accuracy is also presented for a memory system that is constructed as an interleaved memory. Performance evaluation is carried out through trace-driven simulation and the proposed prefetch scheme reduces 45-63% of the memory access delay time (MADT) for the cache system that does not perform any prefetching.

Original languageEnglish
Pages (from-to)755-772
Number of pages18
JournalJournal of Systems Architecture
Volume44
Issue number9-10
DOIs
Publication statusPublished - 1998 Jan 1

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Data storage equipment
Time delay
Computer systems
Degradation

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture

Cite this

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title = "Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors",
abstract = "The performance of conventional instruction prefetching mechanisms (IPMs) is analyzed in this paper based on two performance factors, i.e., the cache miss ratio and the average access time for successfully prefetched blocks. Although significant performance improvement (PI) can be obtained by improving these two factors, most conventional prefetching mechanisms improve only one factor out of these two factors. Fetching multiple blocks for a prefetch request and prefetching the sequentially next block together with the block that causes a cache miss in lookahead prefetching (LP) are proposed to improve both these factors. A new method to initiate a prefetch request earlier with no degradation of the prefetch accuracy is also presented for a memory system that is constructed as an interleaved memory. Performance evaluation is carried out through trace-driven simulation and the proposed prefetch scheme reduces 45-63{\%} of the memory access delay time (MADT) for the cache system that does not perform any prefetching.",
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AU - Kim, Shin-Dug

AU - Yang, Sung-Bong

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